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參數(shù)資料
| 型號(hào)： | KSZ8993MLI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 71/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH 10/100 3PORT 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | * |
| 產(chǎn)品目錄頁面： | 1081 (CN2011-ZH PDF) |
| 其它名稱： | 576-3350 |
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Micrel, Inc.
KSZ8993M/ML
October 2008
73
M9999-020606
Then,
Read reg. 117 (counter value 30-24) // If bit 30 = 0, restart (reread) from this register
Read reg. 118 (counter value 23-16)
Read reg. 119 (counter value 15-8)
Read reg. 120 (counter value 7-0)
3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)
Write to reg. 110 with 0x1d (read MIB counter selected)
Write to reg. 111 with 0x00 (trigger the read operation)
Then
Read reg. 119 (counter value 15-8)
Read reg. 120 (counter value 7-0)
Additional Information
Both “Per Port” and “All Port Dropped Packet” MIB counters do not indicate overflow. The application must keep
track of overflow conditions for these counters.
“All Port Dropped Packet” MIB counters do not indicate if count is valid. The application must keep track of valid
conditions for these counters.
To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are
160 registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2
minutes. It is recommended that the software read all the counters at least every 30 seconds.
A high performance SPI master is also recommended to prevent counters overflow.
Per Port MIB counters are designed as “read clear.” That is, these counters will be cleared after they are read.
“All Port Dropped Packet” MIB counters are not cleared after they are read.
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| KSZ8995MA | 功能描述:以太網(wǎng) IC 5 Port 10/100 Switch with PHY and Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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