參數(shù)資料
型號: KSZ8864RMN-EVAL
廠商: Micrel Inc
文件頁數(shù): 10/111頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8864RMN
標準包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8864RMN
已供物品:
相關(guān)產(chǎn)品: 576-3787-ND - IC ETHERNET SW 4PORT 64QFN
其它名稱: 576-3869
1997 Microchip Technology Inc.
DS30444E - page 107
PIC16C9XX
14.4
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
14.4.1
POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specied. See Electrical Specications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, “
Power-up Trouble Shooting.”
14.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a xed 72 ms nominal
time-out on power-up only, from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A conguration bit is provided to enable/dis-
able the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
14.4.3
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
14.4.4
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator conguration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 14-8,
and
depict
time-out
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 14-9). This is useful for testing purposes or to
synchronize more than one PIC16CXXX device operat-
ing in parallel.
Table 14-5 shows the reset conditions for some special
function registers, while Table 14-6 shows the reset
conditions for all the registers.
14.4.5
POWER CONTROL/STATUS REGISTER
(PCON)
Bit1 is Power-on Reset Status bit POR. It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Conguration
Power-up
Wake-up from SLEEP
PWRTE = 1
PWRTE = 0
XT, HS, LP
1024TOSC
72 ms + 1024TOSC
1024 TOSC
RC
72 ms
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