參數(shù)資料
型號(hào)： KSZ8721BL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 33/35頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8721BL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8721BL
主要屬性： 1 個(gè)端口，100BASE-TX/100BASE-FX/10BASE-T
次要屬性： MII，RMII，HP 自動(dòng) MDI，MDI-X 自動(dòng)極性校正
已供物品： 板
相關(guān)產(chǎn)品： 576-1028-6-ND - IC TXRX PHY 10/100 3.3V 48LQFP
576-1026-6-ND - IC TXRX PHY 10/100 2.5V 48SSOP
KSZ8721BLIA4 TR-ND - TRANSCEIVER 10/100 3.3V 48-LQFP
KSZ8721BLI TR-ND - TXRX PHY 10/100 2.3.3/5V 48-LQFP
KSZ8721BI TR-ND - TXRX PHY 10/100 2.3.3/5V 48-SSOP
KSZ8721BLA4 TR-ND - TXRX 10/100 3.3V 48-SSOP
KSZ8721BLA4-ND - TXRX 10/100 3.3V 48-SSOP
KSZ8721BA4 TR-ND - TXRX 10/100 3.3V 48-SSOP
KSZ8721BA4-ND - TXRX 10/100 3.3V 48-SSOP
576-1028-1-ND - IC TXRX PHY 10/100 3.3V 48LQFP
更多...
其它名稱： 576-1626
Micrel, Inc.
KS8721BL/SL
June 2009
7
M9999-062509-1.3
Pin Description
Pin Number
Pin Name
Type
(1)
Pin Function
1
MDIO
I/O
Management Independent Interface (MII) Data I/O. This pin requires an external 4.7K
pull-up resistor.
2
MDC
I
MII Clock Input. This pin is synchronous to the MDIO.
3
RXD3/
PHYAD
Ipd/O
MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See “Strapping
Options” section for details.
4
RXD2/
PHYAD2
Ipd/O
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See “Strapping
Options” section for details.
5
RXD1/
PHYAD3
Ipd/O
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[3]. See “Strapping
Options” section for details.
6
RXD0/
PHYAD4
Ipd/O
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[4]. See “Strapping
Options” section for details.
7
VDDIO
P
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage regulator. See
“Circuit Design Ref. for Power Supply" section for details.
8
GND
Gnd
Ground.
9
RXDV/
CRSDV/
PCS_LPBK
Ipd/O
MII Receive Data Valid Output.
During reset, the pull-up/pull-down value is latched as PCS_LPBK. See “Strapping
Options” section for details.
10
RXC
O
MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
11
RXER/ISO
Ipd/O
MII Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See
“Strapping Options” section for details.
12
GND
Gnd
Ground.
13
VDDC
P
Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply" section
for details.
14
TXER
Ipd
MII Transmit Error Input.
15
TXC/
REFCLK
I/O
MII Transmit Clock Output.
Input for crystal or an external 50MHz clock. When REFCLK pin is used for REF clock
interface, pull up XI to VDDPLL 2.5V via 10k resistor and leave XO pin unconnected.
16
TXEN
Ipd
MII Transmit Enable Input.
17
TXD0
Ipd
MII Transmit Data Input.
18
TXD1
Ipd
MII Transmit Data Input.
19
TXD2
Ipd
MII Transmit Data Input.
20
TXD3
Ipd
MII Transmit Data Input.
21
COL/
RMII
Ipd/O
MII Collision Detect Output.
During reset, the pull-up/pull-down value is latched as RMII select. See “Strapping
Options” section for details.
22
CRS/
RMII_BTB
Ipd/O
MII Carrier Sense Output.
During reset, the pull-up/pull-down value is latched as RMII back-to-back mode when
RMII mode is selected. See “Strapping Options” section for details.
23
GND
Gnd
Ground.
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