參數(shù)資料
型號(hào)： KSZ8051RNL TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 5/59頁(yè)
文件大?。?/td> 0K
描述： TXRX PHY 10/T100 3.3V RMII 32QFN
特色產(chǎn)品： KSZ8051/8031/8021 Series
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： RMII
電源電壓： 1.8V，2.5V，3.3V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： 576-3778-6
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
13
M9999-070910-1.0
Strapping Options – KSZ8051MNL
Pin Number
Pin Name
Type
(1)
Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipu/O
The PHY Address is latched at de-assertion of reset and is configurable to any value
from 0 to 7.
The default PHY Address is 00001.
PHY Address 00000 is enabled only if the B-CAST_OFF strapping pin is pulled high.
PHY Address bits [4:3] are set to ‘00’ by default.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0]
Mode
000
MII (default)
110
MII Back-to-Back
001 – 101, 111
Reserved – not used
20
ISO
Ipd/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement)
as the Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
At the de-assertion of reset, this pin value is latched into register 0h bit 8.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
At the de-assertion of reset, this pin value is latched into register 0h bit 12.
19
B-CAST_OFF
Ipd/O
Broadcast Off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21
NAND_Tree#
Ipu/Opu
NAND Tree Mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Note:
1.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset,
and consequently cause the PHY strap-in pins on the MII signals to be latched to the unintended high/low states. In this case, external pull-ups (4.7K) or
pull-downs (1.0K) should be added on these PHY strap-in pins to ensure the intended values are strapped-in correctly.
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