參數(shù)資料
型號： KSZ8041TL-S
廠商： Micrel Inc
文件頁數(shù)： 10/65頁
文件大?。?/td> 0K
描述： IC TXRX PHY 10/100 BASE 48TQFP
標準包裝： 250
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 1/1
規(guī)程： SMII
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應商設備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 576-3626
KSZ8041TL-S-ND
Micrel, Inc.
KSZ8041TL/FTL/MLL
December 2009
18
M9999-120909-1.2
Pin Description– KSZ8041MLL
Pin Number
Pin Name
Type
(1)
Pin Function
1
GND
Gnd
Ground
2
GND
Gnd
Ground
3
GND
Gnd
Ground
4
VDDA_1.8
P
1.8V analog VDD
5
VDDA_1.8
P
1.8V analog VDD
6
V1.8_OUT
P
1.8V output voltage from chip
7
VDDA_3.3
P
3.3V analog VDD
8
VDDA_3.3
P
3.3V analog VDD
9
RX-
I/O
Physical receive or transmit signal (- differential)
10
RX+
I/O
Physical receive or transmit signal (+ differential)
11
TX-
I/O
Physical transmit or receive signal (- differential)
12
TX+
I/O
Physical transmit or receive signal (+ differential)
13
GND
Gnd
Ground
14
XO
O
Crystal feedback
This pin is used only when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used.
15
XI
I
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
16
REXT
I/O
Set physical transmit output current
Connect a 6.49K resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041MLL reference schematic.
17
GND
Gnd
Ground
18
MDIO
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7Kpull-up resistor.
19
MDC
I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
20
RXD3 /
PHYAD0
Ipu/O
MII Mode:
Receive Data Output[3]
(2)
/
Config. Mode:
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
21
RXD2 /
PHYAD1
Ipd/O
MII Mode:
Receive Data Output[2]
(2)
/
Config. Mode:
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
22
RXD1 /
PHYAD2
Ipd/O
MII Mode:
Receive Data Output[1]
(2)
/
Config. Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
23
RXD0 /
DUPLEX
Ipu/O
MII Mode:
Receive Data Output[0]
(2)
/
Config Mode:
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
24
GND
Gnd
Ground
25
VDDIO_3.3
P
3.3V digital VDD
26
VDDIO_3.3
P
3.3V digital VDD
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參數(shù)描述
KSZ8051MLL 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (48-LQFP) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8051MLL TR 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (48-LQFP) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8051MLL-EVAL 功能描述:以太網(wǎng)開發(fā)工具 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (48-LQFP) - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
KSZ8051MLLI 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (48-LQFP, Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8051MLLI TR 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (48-LQFP, Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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