參數(shù)資料
型號： KSZ8041NLI TR
廠商： Micrel Inc
文件頁數(shù)： 19/54頁
文件大?。?/td> 0K
描述： IC TXRX PHY 10/100 LV/LP 32-MLF
特色產(chǎn)品： Micrel Drives Ethernet Into the Global Automotive World
標準包裝： 1
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 1/1
規(guī)程： MII，RMII
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，32-MLF?
供應商設(shè)備封裝： 32-MLF?（5x5）
包裝： 標準包裝
產(chǎn)品目錄頁面： 1080 (CN2011-ZH PDF)
配用： 576-1621-ND - BOARD EVALUATION FOR KSZ8041NL
其它名稱： 576-2109-6
Micrel, Inc.
KSZ8041NL/RNL
September 2010
26
M9999-090910-1.4
RMII Signal Definition
The Tables 3 and 4 describe the RMII signals for KSZ8041NL and KSZ8041RNL. Refer to RMII Specification for detailed
information.
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
Description
REF_CLK
Input
Input, or Output
Synchronous 50 MHz clock reference for
receive, transmit and control interface
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RX_ER
Output
Input, or (not required)
Receive Error
Table 3. RMII Signal Description – KSZ8041NL
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041RNL signal)
Direction
(with respect to MAC)
Description
REF_CLK
Output
Input
Synchronous 50 MHz clock reference for
receive, transmit and control interface
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RX_ER
Output
Input, or (not required)
Receive Error
Table 4. RMII Signal Description – KSZ8041RNL
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and
RX_ER.
The KSZ8041NL inputs the 50MHz REF_CLK from the MAC or system board.
The KSZ8041RNL generates the 50MHz RMII REF_CLK and outputs it to the MAC.
Transmit Enable (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final di-bit of a frame.
TX_EN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is ”00” to indicate idle when TX_EN is de-asserted. Values other than “00” on TXD[1:0]
while TX_EN is de-asserted are ignored by the PHY.
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