
Micrel, Inc.
KS8993M/ML/MI
April 2005
38
M9999-041205
Rate Limiting Support
The KS8993M supports hardware rate limiting independently on the “receive side” and on the “transmit side” on a
per port basis. Rate limiting is supported in both priority and non-priority environment. The rate limit starts from 0
kbps and goes up to the line rate in steps of 32 kbps. The KS8993M uses “one second” as the rate limiting
interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to
count the number of bytes during the interval.
On the “receive side”, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets
on the port until the “one second” interval expires. Flow control can be enabled to prevent packet loss. If the rate
limit is programmed greater than or equal to 128 kbps and the byte counter is 8 Kbytes below the limit, flow
control will be triggered. If the rate limit is programmed lower than 128 kbps and the byte counter is 2 Kbytes
below the limit, flow control will also be triggered.
On the “transmit side”, if the number of bytes exceeds the programmed limit, the switch will stop transmitting
packets on the port until the “one second” interval expires.
If priority is enabled, the KS8993M can be programmed to support different rate limits for high priority packets and
low priority packets.
Configuration Interface
The KS8993M can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KS8993M is typically programmed using an EEPROM. If no EEPROM is present, the
KS8993M is configured using its default register settings. Some defaults settings are configured via strap-in pin
options. The strap-in pins are indicated in the “KS8993M Pin Description and I/O Assignment” table.
I
2C Master Serial Bus Configuration
With an additional I
2C (“2-wire”) EEPROM, the KS8993M can perform more advanced switch features like
“broadcast storm protection” and “rate control” without the need of an external processor.
For KS8993M I
2C Master configuration, the EEPROM stores the configuration data for register 0 to register 109
(as defined in the KS8993M register map) with the exception of the “Read Only” status registers. After the de-
assertion of reset, the KS8993M will sequentially read in the configuration data for all 110 registers, starting from
register 0. The configuration access time (tprgm) is less than 15 ms, as depicted in the following figure.
....
RST_N
SCL
SDA
t
prgm<15 ms
Figure 7. KS8993M EEPROM Configuration Timing Diagram
The following is a sample procedure for programming the KS8993M with a pre-configured EEPROM:
1.
Connect the KS8993M to the EEPROM by joining the SCL and SDA signals of the respective devices. For the
KS8993M, SCL is pin 97 and SDA is pin 98.