參數(shù)資料
型號： KS8993MI
廠商： Micrel Inc
文件頁數(shù)： 78/85頁
文件大?。?/td> 0K
描述： IC SWITCH 10/100 3PORT 128PQFP
標準包裝： 66
系列： *
類型： *
應用： *
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應商設備封裝： 128-PQFP（14x20）
包裝： 散裝
配用： 576-1013-ND - BOARD EVAL EXPERIMENT KS8993M
其它名稱： 576-1014
Micrel, Inc.
KS8993M/ML/MI
April 2005
8
M9999-041205
List of Figures
Figure 1. Typical Straight Cable Connection .......................................................................................................................................24
Figure 2. Typical Crossover Cable Connection ...................................................................................................................................24
Figure 3. Auto Negotiation and Parallel Operation .............................................................................................................................25
Figure 4. Destination Address Lookup Flow Chart, Stage 1 ..............................................................................................................27
Figure 5. Destination Address Resolution Flow Chart, Stage 2 ........................................................................................................28
Figure 6. 802.1p Priority Field Format ..................................................................................................................................................37
Figure 7. KS8993M EEPROM Configuration Timing Diagram ............................................................................................................38
Figure 8. SPI Write Data Cycle...............................................................................................................................................................41
Figure 9. SPI Read Data Cycle ...............................................................................................................................................................41
Figure 10. SPI Multiple Write..................................................................................................................................................................41
Figure 11. SPI Multiple Read..................................................................................................................................................................42
Figure 12. Loopback Path ......................................................................................................................................................................43
Figure 13. EEPROM Interface Input Timing Diagram ..........................................................................................................................76
Figure 14. EEPROM Interface Output Timing Diagram .......................................................................................................................76
Figure 15. SNI Input Timing Diagram....................................................................................................................................................77
Figure 16. SNI Output Timing Diagram.................................................................................................................................................77
Figure 17. MAC-Mode MII Timing – Data Received from MII ..............................................................................................................78
Figure 18. MAC-Mode MII Timing – Data Input to MII ..........................................................................................................................78
Figure 19. PHY-Mode MII Timing – Data Received from MII ...............................................................................................................79
Figure 20. PHY-Mode MII Timing – Data Input to MII ...........................................................................................................................79
Figure 21. SPI Input Timing....................................................................................................................................................................80
Figure 22. SPI Output Timing.................................................................................................................................................................81
Figure 23. Reset Timing .........................................................................................................................................................................82
128-Pin PQFP Package ...........................................................................................................................................................................85
List of Tables
Table 1. FX and TX Mode Selection ......................................................................................................................................................21
Table 2. MDI/MDI-X Pin Definitions........................................................................................................................................................22
Table 3. MII Signals .................................................................................................................................................................................30
Table 4. SNI Signals ................................................................................................................................................................................31
Table 5. MII Management Interface Frame Format ..............................................................................................................................32
Table 6. Serial Management Interface (SMI) Frame Format................................................................................................................32
Table 7. Upstream Special Tagging Mode Format ..............................................................................................................................34
Table 8. STPID Egress Rules (Switch Port 3 to Processor)................................................................................................................34
Table 9. FID+DA Lookup in VLAN Mode ...............................................................................................................................................36
Table 10. FID+SA Lookup in VLAN Mode .............................................................................................................................................36
Table 11. KS8993M SPI Connections ....................................................................................................................................................40
Table 12. Format of Static MAC Table (8 Entries)................................................................................................................................66
Table 13. Format of Static VLAN Table (16 Entries) ............................................................................................................................68
Table 14. Format of Dynamic MAC Address Table (1K Entries) ........................................................................................................68
Table 15. Format of “Per Port” MIB Counters......................................................................................................................................69
Table 16. Port 1s “Per Port” MIB Counters Indirect Memory Offsets................................................................................................70
Table 17. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets...............................................................................................71
Table 18. Format of “All Port Dropped Packet” MIB Counters ..........................................................................................................71
Table 19. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets .................................................................................71
Table 20. EEPROM Timing Parameters ................................................................................................................................................76
Table 21. SNI Timing Parameters ..........................................................................................................................................................77
Table 22. MAC-Mode MII Timing Parameters .......................................................................................................................................78
Table 23. PHY-Mode MII Timing Parameters ........................................................................................................................................79
Table 24. SPI Input Timing Parameters ................................................................................................................................................80
Table 25. SPI Output Timing Parameters .............................................................................................................................................81
Table 26. Reset Timing Parameters ......................................................................................................................................................82
Table 27. Transformer Selection Criteria..............................................................................................................................................84
Table 28. Qualified Single Port Magnetics ...........................................................................................................................................84
Table 29. Typical Reference Crystal Characteristics ..........................................................................................................................84
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