參數(shù)資料
型號(hào)： KS88C4504
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mas
中文描述： 新SAM87RC家庭的8位單芯片CMOS微控制器提供了快速，高效的CPU，一個(gè)廣泛的集成外設(shè)，以及各種馬航
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 293K
代理商： KS88C4504
KS88C4504/P4504
PRODUCT OVERVIEW
1-7
Table 1-1. KS88C4504/P4504 Pin Descriptions (Continued)
Pin
Name
Pin
Type
I/O
Pin
Description
Circuit
Type
5
QFP Pin
Number
7
Share
Pins
WAIT
P5.0–P5.1
General I/O port with bit programmable
pins. Normal input or push-pull, output
mode. Alternately It can use as external
interface control signal P5.0/WAIT signal
ADC0–ADC3
I
Analog input pins for A/D converter
module. Alternatively used as general-
purpose I/O
2
49–46
P0.4–P0.7
AV
REF
–
A/D converter reference voltage
AV
SS
is connected to ground internally
Pulse width modulation output pins
50
–
PWM0, PWM1
O
5
23,22
P3.6
P3.7
INT0–INT7
TCCK, TDCK
I
I
External interrupt input pins
External clock input for timer C and timer D
4
3
37–30
28,29
P2.0–P2.7
P3.1/P3.0
TCCAP,TDCAP
I
I
Timer C/ timer D capture input
Input pin for the slow memory timing signal
from the external interface
System reset pin (pull-up resistor: 240 k
)
3
5
26,27
7
P3.3/P3.2
P5.0
WAIT
RESET
I
1
19
–
EA
I
5V: ROMless operating
0V: internal 4K and external 60K
addressing mode
–
16
–
V
DD1
, V
SS1
–
Power input pins for CPU operation
(internal) and Power input for OTP writing
–
12,13
–
V
DD2
, V
SS2
X
IN
, X
OUT
–
Power input pins for port output (external)
–
53,52
–
–
Main oscillator pins
–
15,14
–
SI,SO,
SCK
I/O
synchronous SIO communication port
3
40,39,38
P1.5/P1.6
P1.7
A0–A15
D0–D7
O
I/O
Address output for external device
Data I/O for external device
6
7
65–80
57–64
–
–
PM,DM
O
O
External memory selection output
Memory read/write output
–
–
1,2
3,4
–
–
RD,WR
CS0–CS3
TCOUT,TDOUT
O
O
Embedded chip selection output
16-bit timer PWM mode output
5
5
11–8
25,24
P4.4–P4.7
P3.4, P3.5
VLD
–
Voltage Level Detect Pin
–
5
–
NOTE:
VDD1 must be connected to VDD2 in users application circuit, VSS1 & VSS2 also.
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