參數(shù)資料
型號: KS88C4404
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 8-Bit CMOS Microcontroller(8位 CMOS 微控制器)
中文描述: 8位CMOS微控制器(8位的CMOS微控制器)
文件頁數(shù): 8/14頁
文件大小: 129K
代理商: KS88C4404
KS88C4400/4404 MICROCONTROLLER
DATA SHEET
8-8
System and User Stacks
KS88-series microcontrollers use the system stack
to implement subroutine calls and returns, for
interrupt processing, and for dynamic data storage.
The PUSH and POP instructions support system
stack operations. Hardware support is provided for
stack operations in the internal register file as well
as in external data memory. User stacks can be
freely defined in the register file for dynamic data
storage.
EXTERNAL INTERFACE
The KS88C4400/4404 architecture supports an
external peripheral interface. Instruction code can be
fetched, or data read/write, from external program
memory. If the external program memory is
implemented in a RAM-type device, program code
and data can also be written to external program
memory (by "LDCxx" instructions).
The KS88C4400/4404 microcontroller has a total of
80 pins. Up to 23 pins can be configured as external
interface lines. Because memory addresses that are
carried over the address and data bus are 16 bits,
up to 64 K bytes of data memory and/ or program
memory space can be addressed.
External data memory accesses can be handled
separately from external program memory accesses
by defining (DM and PM) signal line. DM output
remains high level (PM is low level) when
instructions are being fetched or when accessing the
external program memory; DM output goes to low
level whenever an external data memory location is
addressed (by "LDExx" instructions).
INTERRUPTS
The SAM8 interrupt structure has three components:
levels, vectors, and sources. Eight interrupt levels
are recognized by the CPU. Up to 126 vector
addresses are supported for each level. When a
specific interrupt level is assigned more than one
vector address, these vectors are prioritized in
hardware. Each vector may, in turn, have one or
more sources.
The KS88C4400/4404 microcontroller has 20
interrupt sources. Nineteen different vector
addresses are used to support these interrupt
sources. Only seven interrupt levels are used in the
interrupt structure.
When multiple interrupt levels are active, the
interrupt priority register (IPR) determines the order
in which contending interrupts are to be serviced. If
multiple interrupts occur within the same interrupt
level, the interrupt with the lowest vector address is
processed first. The relative priorities of multiple
interrupts within a single level are set in hardware.
The instruction pointer (IP) is used to control
optional high-speed interrupt processing called
fast
interrupts
. With fast interrupt processing, specific
interrupt service routines be completed in
approximately six clock cycles instead of the usual
22 cycles. For the KS88C4400/4404, fast interrupt
processing is not supported for interrupt levels 1 and
2.
INSTRUCTION SET
The SAM8 instruction set is designed to support a
large register file. It includes 78 arithmetic and
logical operations, including multiply and divide.
Binary-coded decimal (BCD) operations include
decimal adjustment of binary values.
Because I/O control and data registers are mapped
directly into the register file, special I/O instructions
are not necessary. Flexible instructions for bit
addressing, and for rotate and shift operations
complete the powerful data manipulation capabilities
of the instruction set.
CLOCK CIRCUITS
An external crystal produces a maximum 18-MHz
CPU clock in the KS88C4400 and 25–MHz in the
KS88C4404. The X
IN
and X
OUT
pins connect the
external oscillation source to the on-chip clock
circuit. The main oscillator circuit generates the CPU
clock signal. To increase processing speed and to
reduce noise levels, non-divided logic is
implemented for the main clock circuit.
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