參數(shù)資料
型號(hào)： KS88C4400
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 8-Bit CMOS Microcontroller(8位 CMOS 微控制器)
中文描述： 8位CMOS微控制器（8位的CMOS微控制器）
文件頁(yè)數(shù)： 9/14頁(yè)
文件大?。?/td> 129K
代理商： KS88C4400
DATA SHEET
KS88C4400/4404 MICROCONTROLLER
8-9
RESET
and POWER-DOWN MODES
A reset is initiated by holding the signal at the
RESET
pin to low level for at least 22 CPU clocks
during power is supplied.. If the EA pin is held at
high level (5-volt input) prior to a reset, ROM-less
mode is initiated and the external interface is
automatically configured by hardware.
The instruction IDLE invokes Idle mode. In Idle
mode, the CPU "sleeps" while select peripherals
remain active: For the KS88C4400/4404, these
peripherals are the PWM module, serial I/O port,
timers A and B, timers C and D, and external
interrupt logic.
During Idle mode, the contents of system registers,
control registers, and data registers are retained.
Port pins retain the mode (input or output) they had
at the time Idle mode was entered. There are two
ways to release Idle mode: 1) activate an enabled
interrupt, causing a hardware release of Idle mode,
and 2) execute an external reset.
The instruction STOP invokes Stop mode. In Stop
mode, the CPU and all peripherals "sleep" (that is,
the on-chip main oscillator is halted). Data stored in
the internal register file and the current values of
peripheral registers are retained. The only way to
release Stop mode is by executing a reset.
When
RESET
is released and goes high level, the
processor restarts the program from ROM vector
address 0020H.
I/O PORTS
Of the 80 pins in the KS88C4400/4404 package, 64
pins are used for I/O. There are six I/O ports, one
Input port and one output port. Each I/O port can be
configured by software to meet varied system
configuration and design requirements. The CPU
accesses an I/O port directly by writing or reading
the port's data register. For this reason, no special
I/O instructions are required.
Ports 0–2 are configured as address and data lines
and bus signal lines for the external peripheral
interface.
The 8-bit input port can receive analog data for the
A/D converter module, or it can serve as a general
input port (port 7).
TIMER MODULE 0
The KS88C4400/4404 timer module 0 (T0) has two
8-bit timers called timer A and timer B. Each timer
has an 8-bit counter register, an 8-bit data register,
an 8-bit comparator, and a corresponding output pin.
Both timers run continuously.
Timer A and timer B operate in interval mode or in
pulse width modulation (PWM) mode. The LSB of
the T0CON register controls the timer A operating
mode, and the LSB of the TBCON register controls
the operating mode for timer B. Timer A and timer B
are driven by the same clock input. There are two
options for timer clock input: the non-scaled CPU
clock or the CPU clock divided by 1024 (decimal).
TIMER MODULE 1
The KS88C4400/4404 has two 16-bit timer/counters,
called timer C and timer D. Both can be configured
to operate either as timers or as event counters.
Timer module 1 can operate in four different modes:
Mode 0
Mode 1
Mode 2
Mode 3
13-bit timer/counter
16-bit timer/counter
8-bit auto-reload timer/counter
Two 8-bit timer/counters (timer D
disabled)
When used as an interval timer, the corresponding
count register is incremented based on the internal
timer clock rate. The timer clock can be selected as
either an external clock source, or a divided-by-six
CPU clock. When used as an event counter, the
timer's count register is incremented whenever a
1-to-0 transition occurs at its external input pin. The
external input is sampled on every fifth cycle of a
6-cycle CPU clock.
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