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參數(shù)資料
| 型號： | KS8721BL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 2/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX PHY 10/100 3.3V 48LQFP |
| 標準包裝： | 250 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | MII，RMII |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 配用： | 576-1007-ND - BOARD EVAL EXPERIMENT KS8721BL |
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Micrel, Inc.
KS8721BL/SL
June 2009
10
M9999-062509-1.3
Strapping Options
(1)
Pin Number
Pin Name
Type
(2)
Pin Function
6, 5,
4, 3
PHYAD[4:1]/
RXD[0:3]
Ipd/O
25
PHYAD0/
INT#
Ipu/O
PHY Address latched at power-up/reset. The default PHY address is 00001.
9
(3)
PCS_LPBK/
RXDV
Ipd/O
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
11
(3)
ISO/RXER
Ipd/O
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
21
(3)
RMII/COL
Ipd/O
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
22
(3)
RMII_BTB
CRS
Ipd/O
Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
PU = Enable.
27
SPD100/
No FEF/
Ipu/O
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default) =
100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as
LED1 the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28
DUPLEX/
LED2
Ipu/O
Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU (default) =
Full-duplex. If Duplex is pulled up during reset, this pin is also latched as the Duplex
support in register 4h.
29
NWAYEN/
LED3
Ipu/O
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/reset.
PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30
PD#
Ipu
Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
Notes:
1.
Strap-in is latched during power-up or reset.
2.
Ipu = Input with internal pull-up.
Ipd/O = Input with internal pull-down during reset; output pin otherwise.
Ipu/O = Input with internal pull-up during reset; output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and oat information.
3.
Some devices may drive MII pins that are designated as output (PHY) on power-up, resulting in incorrect strapping values latched at reset.
It is recommended that an external pull-down via 1k resistor be used in these applications to augment the 8721’s internal pull-down.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KS8721BL A4 | 制造商:Micrel Inc 功能描述:PHY 1-CH 10Mbps/100Mbps 48-Pin LQFP |
| KS8721BL TR | 功能描述:IC TXRX PHY 10/100 3.3V 48LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:1,140 系列:AU 類型:收發(fā)器 驅動器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
| KS8721BL_11 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver |
| KS8721BLA4 | 功能描述:TXRX 10/100 3.3V 48-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:1,140 系列:AU 類型:收發(fā)器 驅動器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
| KS8721BLA4 TR | 功能描述:TXRX 10/100 3.3V 48-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:1,140 系列:AU 類型:收發(fā)器 驅動器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
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