KS8695P Micrel Pin Name I/O Type(1) Description T17 EROEN/ O/" />
參數(shù)資料
型號(hào)： KS8695PI
廠商： Micrel Inc
文件頁(yè)數(shù)： 24/40頁(yè)
文件大小： 0K
描述： IC ARM9 W/MMU 5PORT 289-PBGA
標(biāo)準(zhǔn)包裝： 84
類型： 網(wǎng)關(guān)
應(yīng)用： 網(wǎng)絡(luò)和通信
安裝類型： 表面貼裝
封裝/外殼： 289-PBGA
供應(yīng)商設(shè)備封裝： 289-PBGA（19x19）
包裝： 管件
配用： KS8695P-MDP-EVAL-ND - EVAL KIT EXPERIMENTAL KS8695PMPD
KS8695-EVAL-ND - EVAL KIT EXPERIMENTAL KS8695
576-1003-ND - BOARD EVAL MULTIMEDIA KS8695P
August 2005
30
M9999-081805
KS8695P
Micrel
Pin
Name
I/O Type(1)
Description
T17
EROEN/
O/I
Normal mode: External I/O and ROM/SRAM/FLASH output enable: Active low.
WRSTPLS
When asserted, this signal controls the output enable port of the specied memory
device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, active low;
WRSTPLS = 1, active high. No default.
M17
ERWEN0/
O
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
TESTACK
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory reserved test signal).
N17
ERWEN1/
O
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
TESTREQB
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory reserved test signal).
P17
ERWEN2/
O
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
TESTREQA
the ERWENx controls the byte write enable of the memory device except SDRAM).
ARM CPU test signal (factory reserved test signal).
R17
ERWEN3/
O
External I/O and ROM/SRAM/FLASH write byte enable. Active low. When asserted,
TICTESTENN
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory reserved test signal).
E15
WLED0/
O/I
Normal mode: WAN LED indicator 0: Programmable via WAN misc. Control register
B0SIZE0
bits [2:0].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SiZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
E14
WLED1/
O/I
Normal mode: WAN LED indicator 1: Programmable via WAN Misc. Control register
B0SIZE1
bits [6:4].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
Factory Test Pins
Pin
Name
I/O Type(1)
Description
F7
TESTEN
I
Factory test signal. Pull-down or direct connect to GND required.
M4
TEST1
I
Factory test signal. No connect for normal operation.
F4
TEST2
I
Factory test signal. No connect for normal operation.
Note:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
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