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參數(shù)資料
| 型號： | KS8001S TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 2/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 10/100 LINKMD 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | IEEE 802 |
| 電源電壓： | 1.8 V ~ 3.3 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | KS8001L-EVAL-ND - EVAL KIT EXPERIMENTAL KS8001L |
| 其它名稱： | KS8001STR KS8001STR-ND |
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KS8001
Micrel
May 2005 – SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
KS8001
MICREL CONFIDENTIAL. DO NOT DISTRIBUTE.
10
Strapping Options
Pin Number
Pin Name
Type
(Note 2)
Description
6,5,
4,3
PHYAD[4:1] /
RXD[0:3]
Ipd/O
25
PHYAD0/
INT#
Ipu/O
PHY Address latched at power-up / reset. The default PHY
address is 00001.
9
PCS_LPBK/
RXDV
Ipd/O
Enables PCS_LPBK mode at power-up / reset.
PD (default) = Disable, PU = Enable
10
SMII_SELECT
/ RXC
Ipd/O
Enables SMII mode at power-up / reset.
PD (default) = Disable, PU = Enable
11
ISO / RXER
Ipd/O
Enables ISOLATE mode at power-up /reset.
PD (default) = Disable, PU = Enable
21
RMII_SELECT
/ COL
Ipd/O
Enables RMII mode at power-up / reset.
PD (default) = Disable, PU = Enable
22
RMII_BTB/
CRS
Ipd/O
Enable RMII_BTB mode at power-up / reset.
PD (default) = Disable, PU = Enable
27
SPD100 /
No FEF /
LED1
Ipu/O
Latched into Register 0h bit 13 during power-up / reset.
PD = 10Mb/s, PU (default) = 100Mb/s.
If SPD100 is asserted during power-up / reset, this pin also
latched as the Speed Support in register 4h. (If FXEN is
pulled up, the latched value 0 means no Far _End _Fault.)
28
DUPLEX/
LED2
Ipu/O
Latched into Register 0h bit 8 during power-up / reset.
PD = Half Duplex, PU (default) = Full duplex.
If Duplex is pulled up during reset, this pin also latched as the
Duplex support in register 4h.
29
NWAYEN/
LED3
Ipu/O
Nway (auto-=Negotiation) Enable
Latched into Register 0h bit 12 during power-up / reset. PD =
Disable Auto-Negotiation, PU (default) = Enable Auto-
Negotiation
30
PD#
Ipu
Power Down Enable
PU (default) = Normal operation, PD = Power down mode
Note: Strap-in is latched during power up or reset. In some systems, the MAC RXD pins may drive high at all times causing the
PHY strap-in to be latched high during power up or system reset. In this case, it is recommended to use a strong pull down to GND
via 1kohm resistor on RXDV, RXC, and RXER pins. Otherwise, the PHY may stay in Isolate or loop back modes.
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