參數(shù)資料
型號(hào)： KS0794
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 160 COM / 160 SEG DRIVER FOR STN LCD
中文描述： 160的COM / 160賽格驅(qū)動(dòng)STN液晶顯示器
文件頁數(shù)： 10/31頁
文件大?。?/td> 268K
代理商： KS0794
160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794
10
FUNCTIONAL DESCRIPTION
BLOCK FUNCTION
. Active Control
In case of segment mode, controls the selection or deselection of the chip. Following a LP
signal, and after the chip select signal is input, a select signal is generated internally until 160
bits of data have been read in.
Once data input has been completed, a select signal for cascade connection is output, and the
chip is deselected.
In case of common mode, controls the input/output data of bidirectional pins.
. SP Conversion & Data Control
In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into
latch circuit, or keep input data which are 1 clock of XCK at 8-bits parallel mode into latch
circuit, after that they are put on the internal data bus 8 bits at a time.
. Data Latch Control
In case of segment mode, selects the state of the data latch which reads in the data bus
signals. The shift direction is controlled by the control logic, for every 16 bits of data read in,
the selection signal shifts one bit based on the state of the control circuit.
. Data Latch
In case of segment mode, latches the data on the data bus. The latched state of each LC
driver output pin is controlled by the control logic and the data latch control, 160 bits of data
are read in 20 sets of 8 bits.
. Line Latch / Shift Register
In case of segment mode, all 160 bits which have been read into the data latch are
simultaneously latched on the falling edge of the LP signal, and output to the level shifter block.
In case of common mode, shifts data from the data input pin on the falling edge of the LP
signal.
. Level Shifter
The logic voltage signal is level-shifted to the LC driver voltage level, and output to the driver
block.
. 4-level Driver
Driver the LC driver output pins from the line latch/shift register data, selecting one of 4 levels
(V
0
, V
12
, V
43
, V
5
) based on the S/C, FR and DISPOFFB signals.
. Control Logic
Controls the operation of each block. In case of segment mode, when a LP signal has been
input, all blocks are reset and the control logic waits for the selection signal output from the
active control block.
Once the selection signal has been output, operation of the data latch and data transmission
are controlled, 160 bits of data are read in, and the chip is deselected. In case of common
mode, controls the direction of data shift.
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