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參數(shù)資料
| 型號： | KS0715 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Driver & Controller for STN LCD(STN LCD驅(qū)動器和控制器) |
| 中文描述： | 驅(qū)動程序 |
| 文件頁數(shù)： | 14/50頁 |
| 文件大?。?/td> | 255K |
| 代理商： | KS0715 |
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KS0715 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD
14
DISPLAY DATA RAM (DDRAM)
The display data RAM stores pixel data for the LCD. It is a 65-row ((8 page by 8 bits) + 1) by 132-column
addressable array. Each pixel can be selected when the page and column address is specified. The 65 rows are
divided into 8 pages with 8 lines each, and a ninth page with a single line (DB0 only). Data is read from or written to
the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor
correspond to the LCD common lines as shown in Figure 6.
The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates
independently, data can be written into RAM at the same time as when data is being displayed without causing the
LCD to flicker.
PAGE ADDRESS CIRCUIT
The function of this circuit is to provide a page address to the display data RAM shown in Table 7. It incorporates a
4-bit page address register changed only by the set page instruction. Page address 8 (DB3 is high, but DB2, DB1
and DB0 are low) is a special RAM area for icons, and only display data DB0 is valid. When page address is above
8, it is impossible to access the on-chip RAM.
LINE ADDRESS CIRCUIT
This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Therefore, by
setting the line address repeatedly, it is possible to scroll the screen and switch the page without changing the
contents of the on-chip RAM (refer to Table 7). It incorporates a 6-bit Line Address register which can only be
changed by the Initial display line instruction and a 6-bit counter circuit. At the beginning of each LCD frame, the
contents of a register are copied to the line counter which is increased by the CL signal, and generates the line
address for transferring the 132-bit RAM data to the 100 display data latch circuit. However, display data of icons
are not scrolled because the microprocessor cannot access the line address of icons.
Figure 6. RAM-to-LCD Data Transfer
DB0
0
0
1
–
0
DB1
1
0
0
1
DB2
0
1
1
0
DB3
1
0
1
0
DB4
0
0
0
1
Display Data RAM
COM0
–
COM1
COM2
COM3
COM4
LCD Display
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| KS0759 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:81 COM / 128 SEG DRIVER & CONTROLLER FOR STN LCD |
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