參數(shù)資料
型號(hào): KS0164
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Multimedia Audio(波表合成芯片)
中文描述: 多媒體音響(波表合成芯片)
文件頁數(shù): 6/18頁
文件大?。?/td> 83K
代理商: KS0164
KS0164 MULTIMEDIA AUDIO
6/
19
Pin Name
Pin #
Type
Description
MEMORY INTERFACE
MA[22:0]
38,39
42-62
O
Memory Address Bus Bits [22:0]. This is the external memory address bus.
When accessing static memory devices (ROM/SRAM), these pins will
contain a stable address throughout the entire memory cycle. When
accessing dynamic memory, pins MA[11:0] will contain the multiplexed
DRAM address.
Memory Data Bus Bit [15:0]. This is the external memory data bus.
MD[15:0]
63,64,
67-80
36
I/O
WE1*
O
Memory Upper Byte Write Enable. When this signal is low during an
external memory access, it indicates that data bits MD[15:8] should be
written to the addressed memory device.
Memory Lower Byte Write Enable. When this signal is low during an
external memory access, it indicates that data bits MD[7:0] should be
written to the addressed memory device.
Dynamic Memory Row Address Strobe. This signal is the Row Address
Strobe for all external DRAM. When a DRAM device is addressed, this
signal will be driven low shortly after the row address has been placed on
MA[11:0]. It will also be driven low during ROM/SRAM cycles to provide
CAS-before-RAS refresh for any DRAM devices in the system.
Dynamic Memory Column Address Strobes/Static Memory Chip Selects
[2:0]. Up to three memory devices are supported. Device 0 must be a 16-
bit wide ROM. Devices 1 and 2 may be either static or DRAM, although
both must be the same type. The configuration of devices 1 and 2 is
determined by the MSIZE and MTYPE[1:0] signals. When a DRAM device
is addressed, one of these signals will be driven low shortly after the
column address has been placed on MA0-11. It will also be driven low
during static memory cycles to provide CAS-before-RAS refresh for any
DRAM devices in the system. When a static device is addressed, one of
these signals will be driven low shortly after the address has been placed
on MA0-22.
Memory Type Select. This signal selects the type of memory device to be
connected to CAS1* and/or CAS2*. When tied low, static memory devices
are selected. When tied high, DRAM is selected.
Dynamic Memory Size Select. If the MTYPE signal is tied high, these
signals select the size of the DRAM devices connected to CAS1* and/or
CAS2* as follows:
00b => 64K
01b => 256K
10b => 1M
11b => 4M
Memory Clock. CPU and synthesizer external memory accesses are 1:1
interleaved. This signal indicates which device currently has control of the
memory bus. When low, the CPU has control of the memory bus, when
high, the synthesizer has control of the memory bus.
WE0*
37
O
RAS*
35
O
CAS*[2:0]
32-34
O
MTYPE
82
I
MSIZE[1:0]
83,84
I
MCLK
31
O
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