參數(shù)資料
型號(hào): KS0090i
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Driver & Controller for Dot Matrix LCD(點(diǎn)陣LCD的驅(qū)動(dòng)器和控制器)
中文描述: 驅(qū)動(dòng)程序
文件頁數(shù): 9/45頁
文件大?。?/td> 685K
代理商: KS0090I
26COM/64SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
KS0090i
9
Preliminary
FUNCTION DESCRIPTION
SYSTEM INTERFACE
KS0090i has I
2
C serial interface mode. KS0090i is selected when the higher 7-bit of first byte, which is transferred
from the MPU after the start procedure, matches the 7-bit slave address assigned to A6~A0 pin.
During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. DR or IR
register is selected by setting the RS flag of control bit. The data register(DR) is used as temporary data storage
place for being written into DDRAM/CGRAM/ICONRAM, and one of these RAMs is selected by RAM address
setting instruction. The Instruction register(IR) is used to store instruction code transferred from MPU.
RES: MPU reset
SCL: I
2
C serial clock input
SDA: I
2
C serial data input/output
A6 ~ A0: I
2
C slave address input
I
2
C SERIAL MODE
Allows serial data transfer conforming to the I
2
C serial interface protocol over the serial data line (SDA) and serial
transfer clock line (SCL). Here, KS0090i operates write mode only.
Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must be remain stable during the
high period of the clock pulse. If SDA data line changes at this time, the I
2
C serial interface will be transferred to
start or stop condition.
Start and Stop Conditions
KS0090i initiates serial data transfer with a high-to-low transition of the data line when the clock is high. This is
defined as the start condition. On the contrary, KS0090i finishes serial data transfer with a low-to-high transition of
the data line when the clock is high, which is defined as the stop condition.
Acknowledge
From the start to the stop condition, the number of data bytes transferred from MPU to KS0090i is unlimited. Each
byte formatted with eight bits is followed by an acknowledge bit (ACK). After receiving each 8-bit data, KS0090i
pulls down SDA pin to a low level. At this time the MPU must be generates an extra clock pulse for acknowledge bit
transferred from KS0090i to MPU.
Therefore, if ACK is not returned, the data must be transferred again. A series of data bytes can be transferred so
long as KS0090i does not meet the stop condition.
I
2
C Protocol
KS0090i is selected when the higher 7-bit of first byte, which transferred from the MPU after the start procedure,
matches the 7-bit slave address assigned to A6~A0 pin. After being selected, KS0090i receives the subsequent
data strings.
Table 2. I
2
C Serial Interface
RES
A6 ~ A0
SCL
SDA
RESET
A6 ~ A0
I
2
C clock
I
2
C data
相關(guān)PDF資料
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