參數(shù)資料
型號(hào): KMSC7116VM1000
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 40/60頁(yè)
文件大?。?/td> 0K
描述: DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝: 2
系列: StarCore
類型: 定點(diǎn)
接口: 主機(jī)接口,I²C,UART
時(shí)鐘速率: 266MHz
非易失內(nèi)存: ROM(8 kB)
芯片上RAM: 400kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA
供應(yīng)商設(shè)備封裝: 400-MAPBGA(17x17)
包裝: 托盤(pán)
Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
45
3.2.2.3
Case 3
The power-up sequence is as follows:
1.
Turn on the VDDIO (3.3 V) supply first.
2.
Turn on the VDDC (1.2 V) supply second.
3.
Turn on the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (third).
Note:
Make sure that the time interval between the ramp-up of VDDIO and VDDC is less than 10 ms.
The power-down sequence is as follows:
1.
Turn off the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (first).
2.
Turn off the VDDC (1.2 V) supply second.
3.
Turn of the VDDIO (3.3 V) supply third (last).
Use the following guidelines:
Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down time for VDDC and VDDM is less than 10 ms for
power-up and power-down.
Refer to Figure 32 for relative timing for Case 3.
Figure 32. Voltage Sequencing Case 3
Time
V
o
lt
age
Ramp-down
Ramp-up
VDDIO = 3.3 V
VDDM = 2.5 V
VDDC = 1.2 V
VREF = 1.25 V
<10 ms
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