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| 型號： | KMPC8560VT833LB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/36頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 833MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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12
MPC8560 PowerQUICC III
MOTOROLA
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Communications Processor Module (CPM)
Reliability and serviceability
— Internal code parity
— Parity checking on e500 local bus
3.2
Communications Processor Module (CPM)
The CPM contains features that allow the MPC8560 to excel in a variety of applications targeted for the
networking and telecommunication markets. The MPC8560 CPM is a superset of the MPC8260
PowerQUICC II, with enhanced communications processor (CP) performance. The CPM also has
additional hardware and microcode routines that support high bit rate protocols like ATM (up to 155 Mbps
full-duplex) and fast Ethernet (100 Mbps full-duplex).
Figure 2 shows the major functional units in the MPC8560 CPM.
Figure 2. MPC8560 Communications Processor Module (CPM) Block Diagram
The following list summarizes the major features of the CPM:
The CP is an embedded 32-bit RISC controller residing on a separate bus (CPM local bus). With
this separate bus, the CP does not affect the performance of the e500 core. The CP handles the
lower-layer tasks and DMA control activities, leaving the e500 core free to handle higher-layer
Baud Rate Generators
System Bus
2 MCCs
3 FCCs
4 SCCs
SPI
I2C
4 Timers
Parallel I/O Ports
Bus Interface
SDMA
Dual-Port
RAM
Communications
ROM
Internal Bus
Peripheral Bus
Serial Interface (SI) and Time-Slot Assigner (TSA)
CPM Interrupt
Controller
Local Bus
CPM INT
Processor (CP)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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