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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
62
Freescale Semiconductor
PCI/PCI-X
Figure 36 shows the PCI/PCI-X input AC timing conditions.
Figure 36. PCI/PCI-X Input AC Timing Measurement Conditions
Figure 37 shows the PCI/PCI-X output AC timing conditions.
Figure 37. PCI/PCI-X Output AC Timing Measurement Condition
Table 53 provides the PCI-X AC timing specifications at 66 MHz.
Table 53. PCI-X AC Timing Specifications at 66 MHz
Parameter
Symbol
Min
Max
Unit
Notes
SYSCLK to signal valid delay
tPCKHOV
—
3.8
ns
1, 2, 3, 7, 8
Output hold from SYSCLK
tPCKHOX
0.7
—
ns
1, 10
SYSCLK to output high impedance
tPCKHOZ
—
7
ns
1, 4, 8, 11
Input setup time to SYSCLK
tPCIVKH
1.7
—
ns
3, 5
Input hold time from SYSCLK
tPCIXKH
0.5
—
ns
10
REQ64 to HRESET setup time
tPCRVRH
10
—
clocks
11
HRESET to REQ64 hold time
tPCRHRX
050
ns
11
HRESET high to first FRAME assertion
tPCRHFV
10
—
clocks
9, 11
PCI-X initialization pattern to HRESET setup time
tPCIVRH
10
—
clocks
11
tPCIVKH
CLK
Input
tPCIXKH
CLK
Output Delay
tPCKHOV
High-Impedance
tPCKHOZ
Output