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參數(shù)資料
型號： KMPC8358ZUAGDGA
廠商： Freescale Semiconductor
文件頁數(shù)： 46/95頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II PRO 740TBGA
標準包裝： 2
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 740-LBGA
供應商設備封裝： 740-TBGA（37.5x37.5）
包裝： 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
50
Freescale Semiconductor
I
2C
Figure 33 provides the AC test load for the I2C.
Figure 33. I2C AC Test Load
Figure 34 shows the AC timing diagram for the I2C bus.
Figure 34. I2C Bus AC Timing Diagram
Data hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
02
—
0.93
μs
Rise time of both SDA and SCL signals
tI2CR
20 + 0.1 Cb
4
300
ns
Fall time of both SDA and SCL signals
tI2CF
20 + 0.1 Cb
4
300
ns
Set-up time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1
× OVDD
—V
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2
× OVDD
—V
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I
2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
Table 44. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 43).
Parameter
Symbol1
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Sr
S
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
相關PDF資料
PDF描述
KMPC8358ZQAGDDA IC MPU POWERQUICC II PRO 668PBGA
KMPC8358VVAGDGA IC MPU POWERQUICC II PRO 740TBGA
1-84982-1 CONN FFC 11POS 1.00MM VERT SMD
2-84534-5 CONN FFC 25POS 1.25MM VERT
1-84534-7 CONN FFC 17POS 1.25MM VERT
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