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    參數(shù)資料
    型號(hào): KMPC8349VVAJDB
    廠(chǎng)商: Freescale Semiconductor
    文件頁(yè)數(shù): 23/87頁(yè)
    文件大?。?/td> 0K
    描述: IC MPU PWRQUICC II 672-TBGA
    標(biāo)準(zhǔn)包裝: 2
    系列: MPC83xx
    處理器類(lèi)型: 32-位 MPC83xx PowerQUICC II Pro
    速度: 533MHz
    電壓: 1.2V
    安裝類(lèi)型: 表面貼裝
    封裝/外殼: 672-LBGA
    供應(yīng)商設(shè)備封裝: 672-TBGA(35x35)
    包裝: 托盤(pán)
    MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
    Freescale Semiconductor
    3
    Overview
    Double data rate, DDR1/DDR2 SDRAM memory controller
    — Programmable timing supporting DDR1 and DDR2 SDRAM
    — 32- or 64-bit data interface, up to 400 MHz data rate
    — Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
    — DRAM chip configurations from 64 Mbits to 1 Gbit with ×8/×16 data ports
    — Full error checking and correction (ECC) support
    — Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
    — Contiguous or discontiguous memory mapping
    — Read-modify-write support
    — Sleep-mode support for SDRAM self refresh
    — Auto refresh
    — On-the-fly power management using CKE
    — Registered DIMM support
    — 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
    Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
    — Dual controllers designed to comply with IEEE 802.3, 802.3u, 820.3x, 802.3z,
    802.3ac standards
    — Ethernet physical interfaces:
    – 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
    – 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
    — Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
    programming models
    — 9.6-Kbyte jumbo frame support
    — RMON statistics support
    — Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
    — MII management interface for control and status
    — Programmable CRC generation and checking
    Dual PCI interfaces
    — Designed to comply with PCI Specification Revision 2.3
    — Data bus width options:
    – Dual 32-bit data PCI interfaces operating at up to 66 MHz
    – Single 64-bit data PCI interface operating at up to 66 MHz
    — PCI 3.3-V compatible
    — PCI host bridge capabilities on both interfaces
    — PCI agent mode on PCI1 interface
    — PCI-to-memory and memory-to-PCI streaming
    — Memory prefetching of PCI read accesses and support for delayed read transactions
    — Posting of processor-to-PCI and PCI-to-memory writes
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