
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
JTAG
Figure 26 provides the boundary-scan timing diagram.
Figure 26. Boundary-Scan Timing Diagram
Figure 27 provides the test access port timing diagram.
Figure 27. Test Access Port Timing Diagram
VM = Midpoint Voltage (OVDD/2)
VM
tJTDVKH
tJTDXKH
Boundary
Data Outputs
Boundary
Data Outputs
JTAG
External Clock
Boundary
Data Inputs
Output Data Valid
tJTKLDX
tJTKLDZ
tJTKLDV
Input
Data Valid
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
VM
tJTIVKH
tJTIXKH
JTAG
External Clock
Output Data Valid
tJTKLOX
tJTKLOZ
tJTKLOV
Input
Data Valid
Output Data Valid
TDI, TMS
TDO