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    參數(shù)資料
    型號: KMPC8315ECVRAGDA
    廠商: Freescale Semiconductor
    文件頁數(shù): 10/106頁
    文件大小: 0K
    描述: IC MPU POWERQUICC II 620-PBGA
    標(biāo)準(zhǔn)包裝: 2
    系列: MPC83xx
    處理器類型: 32-位 MPC83xx PowerQUICC II Pro
    速度: 400MHz
    電壓: 1V
    安裝類型: 表面貼裝
    封裝/外殼: 620-BBGA 裸露焊盤
    供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
    包裝: 托盤
    MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
    Freescale Semiconductor
    11
    Electrical Characteristics
    This figure shows the undershoot and overshoot voltages at the interfaces of the MPC8315E.
    Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD
    3.1.3
    Output Driver Characteristics
    This table provides information on the characteristics of the output driver strengths. The values are
    preliminary estimates.
    Note:
    1. The NVDDx_ON are static power supplies and can be connected together.
    2. The NVDDx_OFF are switchable power supplies and can be connected together.
    3. Minimum Temperature is specified with TA;maximum temperature is specified with TJ.
    4. All Power rails must be connected and power applied to the MPC8315 even if the IP interfaces are not used.
    5. All I/O pins should be interfaced with peripherals operating at same voltage level.
    6. This voltage is the input to the filter discussed in Section 26.2, “PLL Power Supply Filteringand not necessarily the voltage
    at the AVDD pin.
    7. All 1V power supplies should be derived from the same source.
    Table 3. Output Drive Capability
    Driver Type
    Output
    Impedance (
    )
    Supply
    Voltage
    Local bus interface utilities signals
    42
    NVDD = 3.3 V
    PCI signals
    25
    DDR signal1
    18
    GVDD = 2.5 V
    DDR2 signal 1
    18
    GVDD = 1.8 V
    Table 2. Recommended Operating Conditions (continued)
    Characteristic
    Symbol
    Recommended
    Value1
    Unit
    Status in D3
    Warm mode
    Note
    GND
    GND – 0.3 V
    GND – 0.7 V
    Not to Exceed 10%
    G/L/NVDD + 20%
    G/L/NVDD
    G/L/NVDD + 5%
    of tinterface
    1
    1. tinterface refers to the clock period associated with the bus clock interface.
    VIH
    VIL
    Note:
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