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參數(shù)資料
| 型號： | KMPC8314CVRAGDA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 28/101頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC II 620-PBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 400MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 620-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 620-PBGA（29x29） |
| 包裝： | 托盤 |
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MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
32
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
9.5
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes interface of
output pin of the SerDes transmitter differential pair features 50-
output impedance. Each input of the
SerDes receiver differential pair features 50-
on-die termination to XCOREVSS. The reference circuit
of the SerDes transmitter and receiver is shown in Figure 48.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of
this eTSEC port can be left floating. The input signals should be terminated based on the guidelines
described in Section 25.4, “Connection Recommendations,” as long as such termination does not violate
the desired POR configuration requirement on these pins, if applicable.
When operating in SGMII mode, the TSEC_GTX_CLK125 clock is not required for this port. Instead,
SerDes reference clock is required on SD_REF_CLK and SD_REF_CLK pins.
9.5.1
DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in
9.5.2
AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK
This table lists the SGMII SerDes reference clock AC requirements. Please note that SD_REF_CLK and
SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
9.5.3
SGMII Transmitter and Receiver DC Electrical Characteristics
characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SD_TX[n] and
SD_TX[n]) as depicted in Figure 16.
Note:
1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected.
2. Asynchronous signals.
3. Inputs need to be stable at least one TMR clock.
Table 34. SD_REF_CLK and SD_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Unit
Note
tREF
REFCLK cycle time
—
8
—
ns
—
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent
REFCLK cycles
——
100
ps
—
tREFPJ
Phase jitter. Deviation in edge location with respect to mean edge location
–50
—
50
ps
—
Table 33. 1588 Timer AC Specifications (continued)
Parameter
Symbol
Min
Max
Unit
Note
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