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參數(shù)資料
| 型號： | KMPC8241TVR200D |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 40/58頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 200MHZ 357-PBGA |
| 標準包裝： | 2 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 200MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應商設備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤 |
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MPC8241 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
45
System Design Information
7.6
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While the TAP controller can be forced to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port, with additional status monitoring signals. The COP
port must independently assert HRESET or TRST to control the processor. If the target system has
independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 27 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not
be used, TRST should be tied to HRESET through a 0-
Ω isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
power-on. Although Freescale recommends that the COP header be designed into the system as shown in
Figure 27, if this is not possible, the isolation resistor will allow future access to TRST in the case where
a JTAG interface may need to be wired onto the system in debug situations.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). Typically, pin 14 is removed
as a connector key.
There is no standardized way to number the COP header shown in Figure 27. Consequently, different
emulator vendors number the pins differently. Some pins are numbered top-to-bottom and left-to-right
while others use left-to-right then top-to-bottom and still others number the pins counter clockwise from
pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 27 is
common to all known emulators.
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