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參數(shù)資料
| 型號(hào)： | KMPC823VR81B2T |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 23/70頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 81MHZ 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 81MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（23x23） |
| 包裝： | 托盤 |
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MPC823 ELECTRICAL SPECIFICATIONS
3
POWER CONSIDERATIONS
The average chip-junction temperature, T
J
,
in
°C can be obtained from
T
J = TA + (PD qJA)
(1)
where
T
A
=
Ambient Temperature,
C
q
JA
=
Package Thermal Resistance, Junction to Ambient,
C/W
P
D
=P
INT + PI/O
P
INT =IDD x VDD
,
WattsChip Internal Power
P
I/O
=
Power Dissipation on Input and Output PinsUser Determined
For most applications P
I/O < 0.3 PINT and can be neglected. If PI/O is neglected
,
an approximate
relationship between P
D and TJ is:
P
D
=K
(T
J + 273C)
(2)
Solving equations (1) and (2) for K gives
K =
P
D (TA + 273C) + qJA PD
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3)
by measuring P
D
(at equilibrium) for a known T
A
. Using this value of K, the values of P
D and TJ
can be obtained by solving equations (1) and (2) iteratively for any value of T
A.
Layout Practices
Each VCC pin on the MPC823 should be provided with a low-impedance path to the boards
supply. Each GND pin should be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to
ground using at least four 0.1
mF bypass capacitors located as close as possible to the four
sides of the package. The capacitor leads and associated printed circuit traces connecting to
chip VCC and GND should be kept to less than half an inch per capacitor lead. A four-layer
board that employs two inner layers as VCC and GND planes should be used.
All output pins on the MPC823 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections
caused by these fast output switching times. This recommendation particularly applies to the
address and data busses. Maximum PC trace lengths of six inches are recommended.
Capacitance calculations should consider all device loads as well as parasitic capacitances
due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical
in systems with higher capacitive loads because these loads create higher transient currents
in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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