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參數(shù)資料
| 型號： | KMM378S203CT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2Mx72 SDRAM DIMM(2Mx72 動態(tài) RAM模塊) |
| 中文描述： | 2Mx72 SDRAM的內(nèi)存（2Mx72動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 154K |
| 代理商： | KMM378S203CT |
SDRAM MODULE
KMM378S203CT
REV. 4 April. '98
Preliminary
PIN NAMES
* These pins are not used in this module.
** These pins should be NC in the system which does not support SPD.
Pin Name
A0~A10
Function
Address Input (multiplexed)
BA0
DQ0 ~ DQ71
CLK0
CKE0
CS0
RAS
CAS
WE
DQM
REGE
SDRAM Bank Select
Data Inputs / Outputs
Clock Input
Clock Enable Input
Chip Select Input
Row Address Storbe
Colume Address Strobe
Write Enable
DQ Mask Enable
Buffer Enable
Unbuffered Physical Detect Input/Output
(separate)
Address input for EEPROM
Serial Data I/O for PD
Clock Input for PD
Power Supply
Power supply for Data Input/Output
Ground
Ground for Data Input/Output
No Connection
*IN, *OUT
**SA0 ~ SA2
**SDA
**SCL
V
DD
V
DDQ
Vss
Vss
Q
NC
INPUT FUNCTION DESCRIPTION
CLK
Clock input
Disables or enables device operation by masking or
enabling all inputs except CLK, CKE and DQM
CS
CKE
Masks system clock to freeze operation from the next
clock cycle. CKE should be enabled at least one cycle
prior to new command.
Disables input buffers for power down standby.
Address
Row & column address are multiplexed on the same
pins.
Row address:RA
0
~RA
10
, Column address:CA
0
~CA
8
BA0
Selects bank to be activated during row address latch
time and selects bank for read/wirte during column
address latch time.
RAS
Latches row address on the positive edge of the CLK
with RAS low. Enables row access & precharge.
CAS
Latches column address on the positive edge of the
CLK with RAS low. Enables column access.
WE
Enables write operation and row precharge.
Latches data in starting from CAS ,WE active.
DQM
Makes data output Hi-Z, tSHZ after the clock and
masks the output. Blocks data intput when DQM active
DQ
Data inputs/outputs are multiplexed on the same pins.
The device operates in the transparent mode when
REGE is low. The A data is latched if CLK is held at a
high or low logic level. If REGE is low, the A-bus data is
stored in the latch/flip-flop on the low-to-high transition
of CLK. REGE is tied to Vcc through 10K ohm Resistor
on PCB. So if REGE of module is floating, this module
will be operated as registered mode.
REGE
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