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參數(shù)資料
| 型號： | KMM375S203CT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2Mx72 SDRAM DIMM(2Mx72 動態(tài) RAM模塊) |
| 中文描述： | 2Mx72 SDRAM的內存（2Mx72動態(tài)內存模塊） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 155K |
| 代理商： | KMM375S203CT |
SDRAM MODULE
KMM375S203CT
Preliminary
REV. 4 May '98
SIMPLIFIED TRUTH TABLE
1. OP Code : Operand Code
A
0
~ A
10
/AP, BA
0
: Program Keys. (@ MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/Self refresh can be issued only at both banks precharge state.
4. BA
0
: Bank Select Address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A
10
/AP is "High" at row precharge, BA
0
is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Wirte DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
(V=Valid, X=Don
′
t Care, H=Logic High, L=Logic Low)
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0
A
10
/AP
A
9
~ A
0
Note
Register
Mode Register Set
H
X
L
L
L
L
X
OP Code
1,2
Refresh
Auto Refresh
H
H
L
L
L
H
X
X
3
Self
Refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Row Address
Read &
Column Address
Auto Precharge Disable
H
X
L
H
L
H
X
V
L
Column
Address
(A
0
~ A
9
)
4
Auto Precharge Enable
H
4,5
Write &
Column Address
Auto Precharge Disable
H
X
L
H
L
L
X
V
L
Column
Address
(A
0
~ A
9
)
4
Auto Precharge Enable
H
4,5
Burst Stop
H
X
L
H
H
L
X
X
6
Precharge
Bank Selection
H
X
L
L
H
L
X
V
L
X
Both Banks
X
H
Clock Suspend or
Active Power Down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Precharge Power Down Mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
V
V
V
DQM
H
V
X
7
No Operation Command
H
X
H
X
X
X
X
X
L
H
H
H
RP
after the end of burst.
Note :
X
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