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參數(shù)資料
| 型號： | KM736V799 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36-Bit Synchronous Pipelined Burst SRAM(128Kx36位同步流水線脈沖靜態(tài) RAM) |
| 中文描述： | 128K × 36至位同步流水線突發(fā)靜態(tài)存儲器（128K × 36至位同步流水線脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 2/17頁 |
| 文件大小： | 404K |
| 代理商： | KM736V799 |
KM736V799
128Kx36 Synchronous SRAM
- 2 -
Rev 2.0
July. 1998
WEc
WEd
OE
ZZ
128Kx36-Bit Synchronous Pipelined Burst SRAM
The KM736V799 is a 4,718,592-bit Synchronous Static Ran-
dom Access Memory designed for high performance second
level cache of Pentium and Power PC based System.
It is organized as 128K words of 36bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applica-
tions; GW, BW, LBO, ZZ. Write cycles are internally self-timed
and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system
′
s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM736V799 is fabricated using SAMSUNG
′
s high perfor-
mance CMOS technology and is available in a 100pin TQFP
and 119BGA package. Multiple power and ground pins are uti-
lized to minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
V
DD
= 3.3V
±
5% Power Supply
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 1cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEa
WEb
DQa
0
~ DQd
7
DQPa ~ DQPd
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
128Kx36
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
DATA-IN
REGISTER
BUFFER
C
R
C
R
A
′
0
~A
′
1
A
0
~A
1
A
2
~A
16
A
0
~A
16
FAST ACCESS TIMES
Parameter
Symbol -44
-50
-55
-57
Unit
Cycle Time
t
CYC
4.4 5.0 5.4 5.7
ns
Clock Access Time
t
CD
3.1 3.1 3.1 3.3
ns
Output Enable Access Time
t
OE
3.1 3.1 3.1 3.3
ns
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