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參數資料
| 型號： | KM732V696 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Kx32 Synchronous SRAM |
| 中文描述： | 64Kx32同步SRAM |
| 文件頁數： | 8/16頁 |
| 文件大?。?/td> | 497K |
| 代理商： | KM732V696 |
PRELIMINARY
KM732V696/L
64Kx32 Synchronous SRAM
Rev 1.0
- 8 -
May 1997
TEST CONDITIONS
(T
A
=0 to 70
°
C, V
DD
=3.3V-5%/+10%, V
DDQ
=3.3V-5%/+10%, or V
DD
=3.3V
±
5%, V
DDQ
=2.5V+0.4V/-0.13V)
Parameter
Value
Input Pulse Level (for 3.3V I/O)
0 to 3V
Input Pulse Level (for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
2ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
2ns
Input and Output Timing Reference Levels(for 3.3V I/O)
1.5V
Input and Output Timing Reference Levels(for 2.5V I/O)
V
DDQ
/2
Output Load
See Fig. 1
Output Load(A)
Output Load(B), (3.3V I/O)
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
Z0=50
Dout
353
5pF*
+3.3V
319
* Capacitive Load consists of all components of
the test environment.
Fig. 1
30pF*
* Including Scope and Jig Capacitance
Output Load(C), (2.5V I/O)
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
1538
5pF*
+2.5V
1667
* Including Scope and Jig Capacitance
RL=50
VL=1.5V for 3.3V I/O
V
DDQ
/2 for 2.5V I/O
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