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參數(shù)資料
| 型號： | KM732V599L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Kx32 Synchronous SRAM |
| 中文描述： | 32Kx32同步SRAM |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 484K |
| 代理商： | KM732V599L |
PRELIMINARY
Rev 1.0
KM732V599A/L
32Kx32 Synchronous SRAM
- 2 -
May 1997
WEc
WEd
OE
ZZ
32Kx32-Bit Synchronous Pipelined Burst SRAM
FEATURES
Synchronous Operation.
2Stage Pipelined operation with 4Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
V
DD
= 3.3V-5%/+10% Power Supply
5V Tolerant Inputs except I/O Pins
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a
linear burst.
Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 1cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A
The KM732V599A/L is a 1,048,576-bit Synchronous Static
Random Access Memory designed for high performance sec-
ond level cache of Pentium and Power PC based System.
It is organized as 32K words of 32 bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applica-
tions; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system
′
s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM732V599A/L is fabricated using SAMSUNG
′
s high per-
formance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
GENERAL DESCRIPTION
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEa
WEb
DQa
0
~ DQd
7
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
32Kx32
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
DATA-IN
REGISTER
BUFFER
C
R
C
R
A
′
0
~A
′
1
A
0
~A
1
A
2
~A
14
A
0
~A
14
FAST ACCESS TIMES
Parameter
Symbol
-7
-8
-10 Unit
Cycle Time
t
CYC
7.5
8.6
10
ns
Clock Access Time
t
CD
4.5
5.0
5.0
ns
Output Enable Access Time
t
OE
4.5
5.0
5.0
ns
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