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參數(shù)資料
| 型號： | KM732V599A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Kx32 Synchronous SRAM |
| 中文描述： | 32Kx32同步SRAM |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 484K |
| 代理商： | KM732V599A |
PRELIMINARY
Rev 1.0
KM732V599A/L
32Kx32 Synchronous SRAM
- 7 -
May 1997
DC ELECTRICAL CHARACTERISTICS
(V
DD
=3.3V-5%+10%, T
A
=0 to 70
°
C)
* V
IL
(Min)=-3.0V(Pulse Width
≤
20ns)
** In Case of I/O Pins, the Max. V
IH
=V
DDQ
+ 0.5V
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current(except ZZ)
I
IL
V
DD
=Max, V
IN
=V
SS
to V
DD
-2
+2
μ
A
μ
A
Output Leakage Current
I
OL
Output Disabled,
V
OUT
=
V
SSQ
to V
DDQ
-2
+2
Operating Current
I
CC
Device Selected, I
OUT
=0mA, ZZ
≤
V
IL
, All
Inputs=V
IL
or V
IH
Cycle Time
≥
t
CYC
Min
-7
-
270
mA
-8
-
260
-10
-
240
Standby Current
I
SB
Device deselected, I
OUT
=0mA, ZZ
≤
V
IL
,
f=Max, All Inputs
≤
0.2V or
≥
V
DD
-0.2V
-7
-
60
mA
-8
-
60
-10
-
60
I
SB1
Device deselected, I
OUT
=0mA,
ZZ
≤
0.2V, f=0,
All Inputs=fixed(V
DD
-0.2V or 0.2V)
-
10
mA
L-Ver.
-
1.0
mA
I
SB2
Device deselected, I
OUT
=0mA,
ZZ
≥
V
DD
-0.2V, f=Max,
All Inputs
≤
V
IL
or
≥
V
IH
-
10
mA
L-Ver.
-
500
μ
A
Output Low Voltage
V
OL
I
OL
=8.0mA
-
0.4
V
Output High Voltage
V
OH
I
OH
=-4.0mA
2.4
-
V
Input Low Voltage
V
IL
-0.5*
0.8
V
Input High Voltage
V
IH
2.0
5.5**
V
TEST CONDITIONS
(T
A
=0 to 70
°
C, V
DD
=3.3V-5%/+10%unless otherwise specified)
Parameter
Value
Input Pulse Level
0 to 3V
Input Rise and Fall Time(Measured at 0.3V and 2.7V)
2ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Fig. 1
Output Load(A)
Output Load(B)
(for t
LZC
, t
LZOE,
t
HZOE
& t
HZC
)
Dout
353
5pF*
+3.3V
319
* Capacitive Load consists of all components of
the test environment.
Fig. 1
* Including Scope and Jig Capacitance
Dout
Z0=50
VL=1.5V
30pF*
RL=50
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