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參數(shù)資料
| 型號(hào)： | KM684000CLT-5L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Quadruple Bilateral Analog Switch 14-PDIP -40 to 85 |
| 中文描述： | 512Kx8位低功耗CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大小： | 169K |
| 代理商： | KM684000CLT-5L |
KM684000C Family
CMOS SRAM
Revision 1.0
April 1999
6
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
Address
OE
Data ou
t
NOTES (
READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
t
OH
t
AA
t
CO1
t
OLZ
t
LZ
t
OHZ
t
HZ
t
RC
t
OE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM684000CLT-7L | Quadruple Bilateral Analog Switch 14-PDIP -40 to 85 |
| KM684000CLTI-5L | 512Kx8 bit Low Power CMOS Static RAM |
| KM684000CLTI-7L | 512Kx8 bit Low Power CMOS Static RAM |
| KM684000CLG-5 | 512Kx8 bit Low Power CMOS Static RAM |
| KM684000CLG-5L | 512Kx8 bit Low Power CMOS Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM684000CLT-7L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx8 bit Low Power CMOS Static RAM |
| KM684000CLTGI-7L | 制造商:Samsung Semiconductor 功能描述: |
| KM684000CLTI-5L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx8 bit Low Power CMOS Static RAM |
| KM684000CLTI-7L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx8 bit Low Power CMOS Static RAM |
| KM684000L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx8 BIT HIGH HIGH SPEED CMOS STATIC RAM |
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