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參數(shù)資料
| 型號： | KM684000CLG-5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx8 bit Low Power CMOS Static RAM |
| 中文描述： | 512Kx8位低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 169K |
| 代理商： | KM684000CLG-5 |
KM684000C Family
CMOS SRAM
Revision 1.0
April 1999
7
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
t
CW(2)
t
WR(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
Controlled)
Address
CS
t
WC
t
WR(4)
t
AS(3)
t
WP(1)
t
DW
t
DH
t
OW
t
WHZ
Data Undefined
Data Valid
WE
Data in
Data out
t
DW
t
DH
Data Valid
WE
Data in
Data out
High-Z
High-Z
t
WC
t
AW
t
AS(3)
t
CW(2)
t
WP(1)
t
AW
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, t
WP
is measured from the begining of write
to the end of write.
2. t
CW
is measured from the CS going low to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
V
CC
4.5V
2.2V
V
DR
CS
GND
Data Retention Mode
CS
≥
V
CC
- 0.2V
t
SDR
t
RDR
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