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參數(shù)資料
| 型號： | KM681000BLP-5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K x8 bit Low Power CMOS Static RAM |
| 中文描述： | 128K的x8位低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 192K |
| 代理商： | KM681000BLP-5 |
PRELIMINARY
CMOS SRAM
Revision 0.3
April 1996
KM681000B Family
Address
CS1
Data Valid
CS2
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE (2)
2
Controlled)
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap of low CS
1
, high CS
2
and low WE. A write begins at the latest transition among CS
1
going low, CS
2
going high and WE
going low. A write ends at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP is measured from the beginning or write
to the end of write.
2.
t
CW is measured from the later of CS
1
going low or CS
2
going high to the end of write.
3.
t
AS is measured from the address calid to the beginning of write.
4.
t
WR is measured from the end of write to the address change.
t
WR1 applied in case a write ends at CS
1
, or WE going high,
t
WR2 applied in case a write
ends at CS
2
going to low.
FUNCTIONAL DESCRIPTION
* X means don't care
CS
1
CS
2
WE
OE
Mode
I/O Pin
Current Mode
H
X
X
X
Power Down
High-Z
I
SB
,I
SB1
X
L
X
X
Power Down
High-Z
I
SB
,I
SB1
L
H
H
H
Output Disable
High-Z
I
CC
L
H
H
L
Read
Dout
I
CC
L
H
L
X
Write
Din
I
CC
t
WC
t
CW(2)
t
WR2(4)
t
AW
t
WP(1)
t
DW
t
DH
t
AS(3)
t
CW(2)
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| KM681000BLP-5L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K x8 bit Low Power CMOS Static RAM |
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