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參數(shù)資料
| 型號： | KM681000BLGI-7L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K x8 bit Low Power CMOS Static RAM |
| 中文描述： | 128K的x8位低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 192K |
| 代理商： | KM681000BLGI-7L |
PRELIMINARY
CMOS SRAM
Revision 0.3
April 1996
KM681000B Family
TEST CONDITIONS
(2. Temperature and Vcc Conditions)
Product Family
Temperature
Power Supply(Vcc)
Speed Bin
Comments
KM681000BL/L-L
0~70
é
5.0V
10%
55/70ns
Commercial
KM681000BLE/LE-L
-25~85
é
5.0V
10%
70/100ns
Extended
KM681000BLI/LI-L
-40~85
é
5.0V
10%
70/100ns
Industrial
PARAMETER LIST FOR EACH SPEED BIN
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
100ns
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
t
AA
55
-
70
-
100
-
ns
Address access time
-
55
-
70
-
100
ns
Chip select to output
t
CO1,
t
CO2
t
OE
t
LZ1,
t
LZ2
t
OLZ
t
HZ1,
t
HZ2
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
-
55
-
70
-
100
ns
Output enable to valid output
-
25
-
35
-
50
ns
Chip select to low-Z output
10
-
10
-
10
-
ns
Output enable to low-Z output
5
-
5
-
5
-
ns
Chip disable to high-Z output
0
20
0
25
0
30
ns
Output disable to high-Z output
0
20
0
25
0
30
ns
Output hold from address change
10
-
10
-
10
-
ns
Write
Write cycle time
55
-
70
-
100
-
ns
Chip select to end of write
45
-
60
-
80
-
ns
Address set-up time
0
-
0
-
0
-
ns
Address valid to end of write
45
-
60
-
80
-
ns
Write pulse width
40
-
50
-
60
-
ns
Write recovery time
0
-
0
-
0
-
ns
Write to output high-Z
0
20
0
25
0
30
ns
Data to write time overlap
25
-
30
-
40
-
ns
Data hold from write time
0
-
0
-
0
-
ns
End write to output low-Z
5
-
5
-
5
-
ns
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| KM681000BLI | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K x8 bit Low Power CMOS Static RAM |
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