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參數(shù)資料
| 型號： | KM62V256D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32K x 8 Bit Low Power CMOS Static RAM(32K x 8位低功耗CMOS 靜態(tài)RAM) |
| 中文描述： | 32K的× 8位低功耗CMOS靜態(tài)RAM（32K的× 8位低功耗的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 140K |
| 代理商： | KM62V256D |
KM62V256D, KM62U256D Family
CMOS SRAM
Revision 1.0
November 1997
5
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
C
L
1)
=30pF+1TTL
1. Refer to AC CHARACTERISTICS
AC CHARACTERISTICS
(KM62V256D Family:Vcc=3.0~3.6V, KM62U256D Family:Vcc=2.7~3.3V
Commercial product :T
A
=0 to 70
°
C, Extended product :T
A
=-25 to 85
°
C, Industrial product :T
A
=-40 to 85
°
C)
1. The parameter is measured with 30pF test load
Parameter List
Symbol
Speed Bins
Units
70
1)
ns
85ns
100ns
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
85
-
100
-
ns
Address access time
t
AA
-
70
-
85
-
100
ns
Chip select to output
t
CO
-
70
-
85
-
100
ns
Output enable to valid output
t
OE
-
35
-
40
-
50
ns
Chip select to low-Z output
t
LZ
10
-
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
30
0
30
0
35
ns
Output disable to high-Z output
t
OHZ
0
30
0
30
0
35
ns
Output hold from address
t
OH
5
-
10
-
15
-
ns
Write
Write cycle time
t
WC
70
-
85
-
100
-
ns
Chip select to end of write
t
CW
60
-
70
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
0
-
ns
Address valid to end of write
t
AW
60
-
70
-
80
-
ns
Write pulse width
t
WP
50
-
60
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
25
0
35
ns
Data to write time overlap
t
DW
30
-
35
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
10
-
10
-
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
≥
Vcc-0.2V
2.0
-
3.6
V
Data retention current
I
DR
Vcc=3.0V, CS
≥
Vcc-0.2V
-
5
μ
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
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