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參數(shù)資料
| 型號： | KM432S2030B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 32Bit x 4 Banks Synchronous DRAM(512K x 32位 x 4 組同步動態(tài)RAM) |
| 中文描述： | 為512k × 32Bit的× 4銀行同步DRAM（512k × 32的位× 4組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 68K |
| 代理商： | KM432S2030B |
KM432S2030B
CMOS SDRAM
REV. 4 July 1998
Preliminary
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit
Note
-8
-L
-10
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
≥
t
RC
(min)
I
OL
= 0 mA
145
140
130
mA
1
Precharge standby current in
power-down mode
I
CC2
P
CKE
≤
V
IL
(max), t
CC
= 15ns
1
mA
I
CC2
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
1
Precharge standby current in
non power-down mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
15
mA
I
CC2
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
6
mA
Active standby current in
power-down mode
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 15ns
3
mA
I
CC3
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
3
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
30
mA
I
CC3
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
20
mA
Operating current
(Burst mode)
I
CC4
I
OL
= 0 mA
Page burst
2 Banks activated
t
CCD
= 2CLKs
3
145
130
130
mA
1
2
130
130
125
Refresh current
I
CC5
t
RC
≥
t
RC
(min)
155
150
140
mA
2
Self refresh current
I
CC6
CKE
≤
0.2V
1
mA
3
450
uA
4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. KM432S2030BT-G**
4. KM432S2030BT-F**
Notes :
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
Input logic high voltage
V
IH
2.0
3.0
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.8
V
2
Output logic high voltage
V
OH
2.4
-
-
V
I
OH
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current (Inputs)
I
IL
-1
-
1
uA
3
Input leakage current (I/O pins)
I
IL
-1.5
-
1.5
uA
3,4
1. V
IH
(max) = 5.6V AC.The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
Notes :
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| KM432S2030C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
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