
KM29U128T, KM29U128IT
FLASH MEMORY
7
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
3. When SE is high, spare area is deselected.
CLE
ALE
CE
WE
RE
SE
WP
Mode
H
L
L
H
X
X
Read Mode
Command Input
L
H
L
H
X
X
Address Input(3clock)
H
L
L
H
X
H
Write Mode
Command Input
L
H
L
H
X
H
Address Input(3clock)
L
L
L
H
L/H
(3)
H
Data Input
L
L
L
H
L/H
(3)
X
Sequential Read & Data Output
L
L
L
H
H
L/H
(3)
X
During Read(Busy)
X
X
X
X
X
L/H
(3)
H
During Program(Busy)
X
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
0V/V
CC
(2)
Stand-by
CAPACITANCE
(
T
A
=25
°
C, V
CC
=3.3V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
VALID BLOCK
NOTE
:
1. The KM29U128 may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid
blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaran-
teed though its initial number could be reduced. (Refer to the attached technical notes)
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
1004
-
1024
Blocks
AC TEST CONDITION
(KM29U128T:T
A
=0 to 70
°
C, KM29U128IT:T
A
=-40 to 85
°
C
,
V
CC
=2.7V~3.6V unless otherwise noted)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL=100pF
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
-
200
500
μ
s
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
2
cycles
Spare Array
-
-
3
cycles
Block Erase Time
t
BERS
-
2
3
ms