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參數(shù)資料
| 型號： | KM23V64005ATY |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64M-Bit (8Mx8 /4Mx16) CMOS Mask ROM(64M位 (8Mx8 /4Mx16) CMOS掩膜ROM) |
| 中文描述： | 6400位（8Mx8 / 4Mx16）的CMOS掩模ROM（6400位（8Mx8 / 4Mx16）的CMOS掩膜光盤） |
| 文件頁數(shù)： | 3/5頁 |
| 文件大小： | 69K |
| 代理商： | KM23V64005ATY |
KM23V64005ATY
CMOS MASK ROM
Preliminary
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
1.5V
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(T
A
=0
°
C to +70
°
C,V
CC
=3.3V/3.0V
±
0.3V, unless otherwise noted.)
READ CYCLE
NOTE
: Page Address is determined as below.
Word mode (BHE=V
IH
) : A
0
, A
1,
A
2
Byte mode (BHE=V
IL
) : A
-1
, A
0
, A
1,
A
2
Item
Symbol
V
CC
=3.3V
±
0.3V
V
CC
=3.0V
±
0.3V
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
100
120
ns
Chip Enable Access Time
t
ACE
100
120
ns
Address Access Time
t
AA
100
120
ns
Page Address Access Time
t
PA
30
40
ns
Output Enable Access Time
t
OE
30
40
ns
Output or Chip Disable to
Output High-Z
t
DF
20
20
ns
Output Hold from Address Change
t
OH
0
0
ns
MODE SELECTION
CE
OE
BHE
Q
15
/A
-1
Mode
Data
Power
H
X
X
X
Standby
High-Z
Standby
L
H
X
X
Operating
High-Z
Active
L
L
H
Output
Operating
Q
0
~Q
15
: Dout
Active
L
Input
Operating
Q
0
~Q
7
: Dout
Q
8
~Q
14
: Hi-Z
Active
CAPACITANCE
(T
A
=25
°
C, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Conditions
MIN
Max
Unit
Output Capacitance
C
OUT
V
OUT
=0V
-
12
pF
Input Capacitance
C
IN
V
IN
=0V
-
12
pF
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