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參數(shù)資料
| 型號： | KM23V32205BSG |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32M-Bit (2Mx16 /1Mx32) CMOS Mask ROM(32M位 (2Mx16 /1Mx32) CMOS掩膜ROM) |
| 中文描述： | 32兆位（2Mx16 / 1Mx32）的CMOS掩模ROM（32兆位（2Mx16 / 1Mx32）的CMOS掩膜光盤） |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 69K |
| 代理商： | KM23V32205BSG |
KM23V32205BSG
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
1.5V
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(T
A
=0
°
C to 70
°
C, V
CC
=3.3V/3.0V0.3V, unless otherwise noted.)
READ CYCLE
NOTE
: Page Address is determined as below.
Double word mode(WORD=V
IH
) ; A
0
, A
1
Word mode(WORD=V
IL
) ; A
-1
, A
0
, A
1
Item
Symbol
KM23V32205BSG-10
KM23V32205BSG-12
KM23V32205BSG-15
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
100
120
150
ns
Chip Enable Access Time
t
ACE
100
120
150
ns
Address Access Time
t
AA
100
120
150
ns
Page Address Access Time
t
PA
30
50
70
ns
Output Enable Access Time
t
OE
30
50
70
ns
Output or Chip Disable to
Output High-Z
t
DF
20
20
30
ns
Output Hold from Address Change
t
OH
0
0
0
ns
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