參數(shù)資料
型號(hào)： KIT33298DWEVB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 3/28頁(yè)
文件大?。?/td> 0K
描述： KIT EVAL FOR MC33298 SMART SW
標(biāo)準(zhǔn)包裝： 1
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
33298
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ARCHIVE
INFORMATION
ARCHIVE
INFORMATION
Figure 7. Valid Data Delay Time and
Valid Time Waveforms
Figure 8. Enable and Disable Time Waveforms
Figure 9. Switching Time Test Circuit
Figure 10. Output Fault Unlatch Disable
Delay Test Circuit
SCLK
SO
(Low-to-High)
(High-to-Low)
tVALID
tDLY(LH)
tDLY(HL)
0.2VDD
0.7VDD
tR (SO)
tF (SO)
0.7VDD
0.2 VDD
0.7VDD
50%
0.2VDD
0
tR (SI)
< 10 ns
< 10ns
tF (SI)
5.0V
V0H
V0L
V0H
V0L
SO (Low-to-High) is for an output with internal conditions such that
the low-to-high transition of CS causes the SO output to switch from
high to low.
90%
10%
90%
CS
SO
(High-to-Low)
(Low-to-High)
0.2VDD
0.7 VDD
< 10 ns
tR(SI)
tF(SI)
tSO(EN)
tSO(DIS)
tSO(EN)
tSO(DIS)
VTri-State
5.0 V
0
tSO(dis)
VTri-State
V0H
1. SO (high-to-low) waveform is for SO output with internal conditions such
that SO output is low except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state, e.g. open load.
2. SO (low-to-high) waveform is for SO output with internal conditions such
that SO output is high except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state, e.g. shortened load.
CL represents the total capacitance of the test fixture and probe.
CS
Output
CL
33298
Under
Test
VDD = 5.0V
VPWR = 14V
RL = 26Ω
CS
Output
CL = 20 pF
33298
Under
Test
VDD = 5.0V
VPWR = 11V
CL represents the total capacitance of the test fixture and probe.
IL = 2.0A
(Output
ΟΝ)
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