參數(shù)資料
型號(hào)： KIC7SZ38FU
廠商： KEC Holdings
英文描述： SILICON MONOLITHIC CMOS DIGITAL INTEGRATED CIRCUIT(2-INPUT NAND GATE)
中文描述： 硅單片CMOS數(shù)字集成電路（2輸入與非門(mén)）
文件頁(yè)數(shù)： 3/3頁(yè)
文件大?。?/td> 524K
代理商： KIC7SZ38FU
2002. 5. 13
3/3
KIC7SZ38FU
Revision No : 0
AC Characteristics (unless otherwise specified, Input : t
r
=t
f
=3ns)
Note : C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption
(I
CCD
) at no output loading and operating at 50% duty cycle. (See Figure2.) C
PD
is related to I
CCD
dynamic operating current
by the expression : I
CCD
=C
PD
V
CC
f
IN
+I
CC
Static
CHARACTERISTIC
SYMBOL
TEST CONDITION
Ta=25
Ta=-40~85
UNIT
V
CC
(V)
1.65
MIN.
TYP.
MAX.
MIN.
MAX.
Propagation delay time
t
PZL
C
L
=50pF,
R
U
=500
R
D
=500
V
I
=2
(Figures 1,3)
V
CC
1.5
6.5
12.7
1.5
13.2
ns
1.8
1.5
5.4
10.5
1.5
11.0
2.5
0.2
0.8
3.5
7.0
0.8
7.5
3.3
0.3
0.8
2.8
5.0
0.8
5.2
5.0
0.5
0.5
2.2
4.3
0.5
4.5
t
PLZ
C
L
=50pF,
R
U
=500
R
D
=500
V
I
=2
(Figures 1,3)
V
CC
1.65
1.5
5.5
12.7
1.5
13.2
ns
1.8
1.5
4.6
10.5
1.5
11.0
2.5
0.2
0.8
3.0
7.0
0.8
7.5
3.3
0.3
0.8
2.1
5.0
0.8
5.2
5.0
0.5
0.5
1.3
4.3
0.5
4.5
Input Capacitance
C
IN
C
OUT
-
0
-
4
-
-
-
pF
Output Capacitance
-
0
-
5
-
-
-
pF
Power Dissipation
Capacitance
C
PD
(Note)
(Figures 2)
3.3
-
5.1
-
-
-
pF
5.0
-
7.3
-
-
-
OUTPUT
INPUT
INPUT
L
C
CC
V
CC
V
RU
RD
tr
tf
90%
50%
10%
V
CC
GND
t
PZL
tw
t
PLZ
INPUT
OUTPUT
OH
V
V
OL
V +0.3V
50%
A
C includes load and stray capacitance
Input PRR=1.0MHz ; t =500ns
FIGURE 1. AC Test Circuit
FIGURE 3. AC Waveforms
Input=AC Waveform ; t =t =1.8ns
PRR=10MHz ; Duty Cycle=50%
FIGURE 2. I Test Circuit
AC Loading and Waveforms
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