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參數(shù)資料
| 型號(hào)： | KH561AM |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Wideband, Low Distortion Driver Amplifier |
| 中文描述： | OP-AMP, 5000 uV OFFSET-MAX, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 182K |
| 代理商： | KH561AM |
KH561
DATA SHEET
REV. 1A February 2001
9
With this total value derived, the required external C
x
is
developed by backing out the effect of the internal 10pF.
This, and an expression for the external C
x
without the
intermediate steps are shown below.
The plot in Figure 6 shows the required C
x
vs. gain for
several desired output impedances using the equations
shown above. Note that for lower R
o
’
s, C
x
can get very
large. But, since the total compensation is actually the
series combination of C
x
and 10pF, going to very high
C
x
’
s is increasingly ineffective as the total compensation
is only slightly changed. This, in part, sets the lower
limits on allowable R
o
.
Figure 6: External Compensation Capacitance (C
x
)
A 0% small signal overshoot response can be achieved
by increasing C
x
slightly from the maximally flat value.
Note that this applies only for small signals due to slew
rate effects coming into play for large, fast edge rates.
Beyond the nominal compensation values developed
thus far, this external C
x
provides a very flexible means
for tailoring the frequency response under a wide variety
of gain and loading conditions. It is oftentimes useful to
use a small adjustable cap in development to determine
a C
x
suitable to the application, then fixing that value for
production. An excellent 5pF to 20pF trimmer cap for this
is a Sprague-Goodman part #GKX20000.
When the KH561 is used to drive a capacitive load, such
as an ADC or SAW device, the load will act to compen-
sate the response along with C
x
. Generally, considerably
lower C
x
values are required than the earlier develop-
ment would indicate. This is advantageous in that a low
R
o
would be desired to drive a capacitive load which,
without the compensating effect of load itself, would
otherwise require very large C
x
values.
Gain and Output Impedance Range
Figure 7 shows a plot of the recommended gain and
output impedances for the KH561. Operation outside of
this region is certainly possible with some degradation in
performance. Several factors contribute to set this range.
At very low output impedances, the required value of
feedback resistor becomes so low as to excessively load
the output causing a rapid degradation in distortion.
The maximum R
o
was set somewhat arbitrarily at 200
.
This allows the KH561 to drive into a 2:1 step down
transformer matching to a 50
load. (This offers
some advantages from a distortion standpoint. See Kota
Application Note KAN-01 for details.)
Figure 7: Recommended Gain and
Output Impedance Range
For a given R
o
, the minimum gain shown in Figure 7 has
been set to keep the equivalent input noise voltage less
than 4nV/
√
Hz. Generally, the equivalent input noise volt-
age decreases with higher signal gains. The high gain
limit has been set by targeting a minimum R
g
of 10
or a
minimum R
f
of 100
.
Amplifier Configurations
The KH561 is intended for a fixed, non-inverting, gain
configuration as shown in Figure 1. The KH560 offers the
better pulse fidelity with its improved thermal tail in the
pulse response (vs. the KH561).
internal forward gain, the inverting node does not present
a low impedance, or virtual ground, node. Hence, in an
inverting configuration, the signal
’
s source impedance
will see a finite load whose value depends on the output
loading. Inverting mode operation can be best achieved
using a wideband, unity gain buffer with low output
impedance, to isolate the source from this varying load.
A DC level can, however, be summed into the inverting
node to offset the output either for offset correction
or signal conditioning.
Due to its low
Accuracy Calculations
Several factors contribute to limit the achievable KH561
accuracy. These include the DC errors, noise effects, and
the impact internal amplifier characteristics have on the
signal gain. Both the output DC error and noise model
may be developed using the equivalent model of Figure
5. Generally, non-inverting input errors show up at the
C
10 C
10
C
or
C
1
R
300 1
2
R
0.08
pF
x
t
t
x
o
g
=
=
C
x
No Load Voltage Gain
0
2
4
6
8
10
12
14
16
18
20
5
10
15
20
25
30
35
40
45
50
55
Maximally Flat Response
into a Matched Load
R
o
= 50
R
o
= 75
R
o
= 100
N
Output Impedance (
)
0
10
20
30
40
50
60
70
80
90
100
0
20
40
60
80
100 120 140 160 180 200
Low R
f
or R
g
Region
Recommended
Region
High Noise Region
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