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    參數(shù)資料
    型號(hào): KFM1216Q2M-DEB
    廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
    英文描述: FLASH MEMORY
    中文描述: 閃存
    文件頁(yè)數(shù): 32/88頁(yè)
    文件大小: 1150K
    代理商: KFM1216Q2M-DEB
    MuxOneNAND512(KFM1216Q2M)
    FLASH MEMORY
    32
    7.8 Start Address1 Register (R/W): F100h, default=0000h
    DFS
    (Device Flash Core Select): it selects Flash Core in two Flash Core of DDP
    FBA
    (NAND Flash Block Address): NAND Flash block address which will be read or programmed or erased.
    15
    14
    13
    12
    11
    10
    9
    8
    7
    6
    5
    4
    3
    2
    1
    0
    DFS
    Reserved(000000)
    FBA
    7.9 Start Address2 Register (R/W): F101h, default=0000h
    DBS
    (Device BufferRAM Select): it selects BufferRAM in two BufferRAM of DDP
    15
    14
    13
    12
    11
    10
    9
    8
    7
    6
    5
    4
    3
    2
    1
    0
    DBS
    Reserved(000000000000000)
    7.10 Start Address3 Register (R/W): F102h, default=0000h
    FCBA
    (NAND Flash Copy Back Block Address): NAND Flash destination block address which will be copy back programmed.
    15
    14
    13
    12
    11
    10
    9
    8
    7
    6
    5
    4
    3
    2
    1
    0
    Reserved(0000000)
    FCBA
    7.11 Start Address4 Register (R/W): F103h, default=0000h
    FCPA
    (NAND Flash Copy Back Page Address): NAND Flash destination page address in a block for copy back program operation.
    FCPA(default value) = 000000
    FCPA range : 000000~111111, 6bits for 64 pages
    FCSA
    (NAND Flash Copy Back Sector Address): NAND Flash destination sector address in a page for copy back program operation.
    FCSA(default value) = 00
    FCSA range : 00~11, 2bits for 4 sectors
    15
    14
    13
    12
    11
    10
    9
    8
    7
    6
    5
    4
    3
    2
    1
    0
    Reserved(00000000)
    FCPA
    FCSA
    Device
    Number of Block
    FBA
    1Gb DDP
    1024
    DFS[15] & FBA[8:0]
    512Mb
    512
    FBA[8:0]
    Comp
    Comp
    DBS=0
    DFS=0
    DDP_OPT
    GND
    CE
    C
    L
    SRAM
    BUFFER
    FLASH
    CORE
    Comp
    Comp
    DBS=1
    DFS=1
    DDP_OPT
    V
    DD
    CE
    C
    L
    SRAM
    BUFFER
    FLASH
    CORE
    CE
    INT
    CHIP 1
    CHIP 2
    INT
    INT
    Figure 4. Chip selection method in DDP
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