
12
KESRX05
operation to the receiver between PDO and PD2 to lower
power consumption of the receiver. When Duty cycling
the receiver between PD1 and PD2 the settling time of the
receiver is independent of C8. In the application circuit
Figures 25 and 26 the value of C8 is configured for
minimum settling time. The times to valid data with C8 =
10nF are shown in Figure 18 for PD0 to PD2 and PD1 to
PD2.
Anti-jamming Circuit
The output of the RSSI is AC coupled by C10 into the Anti-
jamming circuit where the signal is DC restored on the
peak signal level (Figure 10). The coupling capacitor
charges to the appropriate DC level, which is related to
the final slice level for the data comparator. The anti-
jamming circuit amplifies the peak of the signal to recover
the data signal component even in the presence of
jamming signals. The interferer causes modulation of the
wanted signal at the beat frequency of the two signals and
reduces the amplitude of the wanted data component
making it more difficult to recover. The action of the anti-
jamming circuit centres the bandwidth of the receiver
around the wanted signal proportional to the data filter
bandwidth to suppress the interfering beat frequency
recovering the wanted signal. Bypassing the anti-jamming
circuit (Figure 11) will result in data corruption for interfering
RF signal levels 6dB below the wanted signal (Figures 8
and 9).
The DC restoration circuit has a fast attack time and slow
decay time, both controlled by the value of coupling
capacitor chosen between RSSI and DETB pins. Reducing
the data rate or increasing the mark/space ratio will require
a corresponding increrase in the value of C10.
Figure 6 illustrates a suitable test setupforcharacterising
the interference rejection and selectivity of the receiver.
Figure 8 illustrates the in-band interference rejection with
the anti-jam circuit connected as shown in Figure 10 and
bypassed (Figure 11) at V
CC
= 3V and T
AMB
= 25
°
C. Note
the improvement in interference rejection between the two
modes of operation over the wanted signal range of
2
94
to 0dBm. Note also the 40dB improvement in signal
handling capability with the anti- jam circuit connected and
the 20dB improvement with the SAW filter removed
Figure 9 illustrates the difference in receiver selectivity with
the ant-jam circuit connected and bypassed. Note the
improvement in receiver selectivity between the two modes
of operation over the frequency range 433·92MHz
6
5kHz
and the ability of the anti-jam circuit to improce the
selectivity of the SAW filter over the frequency range
433MHz to 434·5MHz. Also note the 20dB improvement
in the in-band signal handling capability demonstrated in
Figure 8 with the SAW filter not used. This can be used to
improve the out-of-band blocking capability of the
application without SAW filter (Figure 25); this design option
can reduce the overall cost of the receiver by, typically, 1
to 2 US Dollars.The selectivity curve with the anti-jam circuit
by-passed is governed by the response of the front end IF
ceramic filter, secondary IF filter and data filter.
Figures 8 and 8 were recorded with the component
specifications given in Table 3.
Component specification (Figure 10)
Component specification (Figure 11)
R6
C2
L5//C7
Data filter BW
IF BW
SAW BW/No SAW BW
OOK modulation
130k
270pF
1MHz at 10·7MHz
5kHz
470kHz
750kHz/1MHz
2kb/s (50% duty cycle)
R6
C2
L5//C7
Data filter BW
IF BW
SAW BW/No SAW BW
OOK modulation
12k
N/A
1MHz at 10·7MHz
5kHz
470kHz
750kHz/1MHz
2kb/s (50% duty cycle)
Table 3 Component specification for Figures 10 and 11. The values given are changes from those given in Table 5
necessary to obtain the results shown in Figures 8 and 9.