參數(shù)資料
型號(hào): KESRX05B1T
廠商: Zarlink Semiconductor Inc.
英文描述: 260 to 470MHz ASK Receiver with Power Down
中文描述: 260至470MHz ASK接收機(jī)的斷電
文件頁數(shù): 6/28頁
文件大?。?/td> 466K
代理商: KESRX05B1T
5
KESRX05
Pin
Name
Function
Schematic
15
16
17
18
19
20
21
DSN
LF
V
EE
VCO2
VCO1
DF2
DF1
Data slice reference level
The DSN pin is defined internally by the Slice volt-
age V
REF
. The DSN slice voltage can be offset from
the internal reference V
REF
by connecting a resistor
from the DSN pin to V
EE
and/or the peak detector
output.
For further information please refer to the Baseband
section of the Functional Description.
PLL loop filter connection
The phase detector output current is derived by two
internal current sources. The nominal linear average
output current is
1
15
μ
A (5
μ
A/radian).
For further information please refer to the Phase Lock
Loop VCO section of the Functional Description
Negative supply
Voltage controlled oscillator
The voltage controlled oscillator circuit is designed
from two cross coupled transistors. The centre fre-
quency of the VCO is set by the external tank circuit.
For further information please refer to the Voltage
Controlled Oscillator (VCO) Circuit Design / Layout
section of the Functional Description
Voltage controlled oscillator
Data Filter Output
The data filter is configured as a unity gain amplifier
with a low impedance output. Tracking of the received
baseband signal is achieved by an internal current
source.
For further information please refer to the Baseband
section of the Functional description.
Cont…
Table 1 Pin descriptions (continued)
HYSTERESIS
25mV
3k
DSN
V
EE
100k
VREF
(V
BE
)
DF2
3k
Data filter input
Input to data filter. Bandwidth of second order Sallen
and Key data filter is set by external components
R10, R1 1, C5 and C6.
For further information please refer to the Baseband
section of the Functional Description.
LF
1
15
μ
A
2
15
μ
A
UP
DOWN
300
μ
A
1·4k
1·4k
50
50
VCO2
VCO1
V
CC
DF1
HYSTERESIS
25mV
3k
DSN
V
EE
100k
VREF
(V
BE
)
DF2
3k
See pin 18
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