參數(shù)資料
型號(hào)： KESRX04
廠商： Zarlink Semiconductor Inc.
英文描述： 260 to 470MHz. ASK Receiver with Power Down
中文描述： 260至470MHz。 ASK接收機(jī)的斷電
文件頁(yè)數(shù)： 7/21頁(yè)
文件大?。?/td> 506K
代理商： KESRX04
7
KESRX04
Voltage Controlled Oscillator (VCO) Circuit Design / Layout
The Local Oscillator (LO) frequency is controlled by a parallel resonant tuned circuit. The frequency of the local oscillator is
controlled by a Phase Locked Loop (PLL), referenced to the crystal frequency.
Designing for VCO Track Parasitics
To remove the effect of track parasitics the following
procedure should be adopted.
1. Open circuit the control feed back from the PLL control
loop by removing R1.
2. Connect an external Power Supply Unit (PSU = VCC/2) in
place of R1, LF output Figure 3.
3. Using a spectrum analyser, monitor the LO level at the RFin
port. Alternatively use a small pick-up coil to loosely couple
to the signal generated across L2.
4. Note :- LO level is < -65 dBm, Range = 300 to 500MHz.
5. Vary the value of the PSU input to confirm that there is a
corresponding change in LO frequency. Set the PSU at
VCC/2. If the VCO does not oscillate at VCC/2, characterise
the LO at an alternative voltage.
6. Using a plot of the varactor characteristic determine the
varactor capacitance at VCC/2. e.g. for a 2 volt VCC design
the Siemens BB833 capacitance at 1Volt = 10pF
(approx.).
7. Using the following equation deduce the value of the total
stray parasitic capacitance (Cp).
Cp =
1
( 2
π
* LO)
2
* L2
((
Cv: Varactor capacitance at Vcc/2
-Cv
)
)
8. Using the following equation select the nearest value for L2
to centre the VCO at VCC/2.
L
LO
Cp
Cv
2
1
2
=
+
(
*
) *(
)
π
9. By varying the PSU voltage confirm that the LO is centred
correctly at VCC/2, and that the oscillator operates over
the range 0 to Vcc.
10. Disconnect the PSU and reconnect R1. Measure the
value at LF output using a x10 probe and an oscilloscope.
This should be a direct voltage with no ripple at VCC/2
(+/- 0.3 volt). If not repeat steps 1 to 8. To compensate for
non standard inductor values vary the value of C18 and
C11 to vary the capacitance of the varactor to centre the
VCO at VCC/2.
Note:
It is important to minimise stray capacitance in the VCO circuit to ensure that the VCO starts oscillating. The use of a varactor
with a low capacitance at zero bias is advisable. Similarly, reducing the values of C11 and C18 whilst increasing L2 will help to
reduce the capacitance of the varactor at 0 volts, improving the reliability of the oscillator
.
A compact design methodology is
recommended for the VCO circuit components L2, C11, C18 and D1.
Figure 3 Characterising the VCO/PLL operation
Phase
Detector
XTAL 1
XTAL1/2 (pins 23/24)
LF (pin 16)
VCO1 (pin 18)
VCO1 (pin 19)
VCO
Buffer
DIV
64
KESRX04
L2
C11
C18
R1
C12
C1
RTest (=R1)
Connect or characterisation
D1
PSU
R2
R4
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KESRX04C/IG/QP1S 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: 制造商:ZARLINK 功能描述:
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KESRX04QP1S 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:260 to 470MHz. ASK Receiver with Power Down
KESRX04QP1T 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:260 to 470MHz. ASK Receiver with Power Down
KESRX05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:260 to 470MHz ASK Receiver with Power Down
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